DS26524 Datasheet, PDF (242/273 Pages) Maxim Integrated Products – Quad T1/E1/J1 Transceiver

DS26524 Quad T1/E1/J1 Transceiver
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode
TSYNC
TSER¹
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
TSIG¹
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
TSER^{2 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32}
TSIG²
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
TSER³
FR4
FR5
FR6
FR7 FR0
FR1
FR2
FR3 FR4
FR5
FR6
FR7 FR0
FR1
FR2
FR3 FR4
FR5
FR6
FR7
Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32
TSIG³
FR4
FR5
FR6
FR7 FR0
FR1
FR2
FR3 FR4
FR5
FR6
FR7 FR0
FR1
FR2
FR3 FR4
FR5
FR6
FR7
Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32 Ch1-32
SYSCLK
TSYNC⁴
TSER
TSIG
Framer 3, Channel 32
LSB MSB
Framer 3, Channel 32
A B C/A D/B
BIT DETAIL
Framer 0, Channel 1
LSB MSB
Framer 0, Channel 1
A B C/A D/B
Framer 0, Channel 2
LSB MSB
Framer 0, Channel 2
A B C/A D/B
AB
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. 16.384 MHz bus configuration.
4. TSYNC is in the input mode (TIOCR.2 = 0).
5. Though not shown, TCHCLK continues to mark the channel LSB for the framers active period.
6. Though not shown, TCHBLK continues to mark the blocked channels for the framers active period.
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