MAX1652 Datasheet, PDF (24/28 Pages) Maxim Integrated Products – High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP

High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
__________Applications Information
Heavy-Load Efficiency Considerations
The major efficiency loss mechanisms under loads (in
the usual order of importance) are:
• P(I²R), I²R losses
• P(gate), gate-charge losses
• P(diode), diode-conduction losses
• P(tran), transition losses
• P(cap), capacitor ESR losses
• P(IC), losses due to the operating supply current
of the IC
Inductor-core losses are fairly low at heavy loads
because the inductor’s AC current component is small.
Therefore, they aren’t accounted for in this analysis.
Ferrite cores are preferred, especially at 300kHz, but
powdered cores such as Kool-mu can work well.
Efficiency = P_OUT / P_IN x 100%
= P_OUT / (P_OUT + P_TOTAL) x 100%
P_TOTAL = P(I²R) + P(gate) + P(diode) + P(tran) +
P(cap) + P(IC)
P(I²R) = (I_LOAD)² x (R_DC + R_DS(ON) + R_SENSE)
where R_DC is the DC resistance of the coil, R_DS(ON) is
the MOSFET on-resistance, and R_SENSE is the current-
sense resistor value. The R_DS(ON) term assumes identi-
cal MOSFETs for the high- and low-side switches
because they time-share the inductor current. If the
MOSFETs aren’t identical, their losses can be estimat-
ed by averaging the losses according to duty factor.
P(gate) = gate-driver loss = qG x f x VL
where VL is the MAX1652 internal logic supply voltage
(5V), and qG is the sum of the gate-charge values for
low- and high-side switches. For matched MOSFETs,
qG is twice the data sheet value of an individual
MOSFET. If V_OUT is set to less than 4.5V, replace VL in
this equation with V_BATT. In this case, efficiency can be
improved by connecting VL to an efficient 5V source,
such as the system +5V supply.
P(diode) = diode conduction losses
= I_LOAD x V_FWD x t_D x f
where t_D is the diode conduction time (120ns typ) and
V_FWD is the forward voltage of the Schottky.
PD(tran) = transition loss =
( ) ^{VBATT x CRSS}
V_BATT x I_LOAD x f x ——————— + 20ns
I_GATE
where C_RSS is the reverse transfer capacitance of the
high-side MOSFET (a data sheet parameter), I_GATE is
the DH gate-driver peak output current (1A typ), and
20ns is the rise/fall time of the DH driver.
P(cap) = input capacitor ESR loss = (I_RMS)² x R_ESR
where I_RMS is the input ripple current as calculated in the
Input Capacitor Value section of the Design Procedure.
Light-Load Efficiency Considerations
Under light loads, the PWM operates in discontinuous
mode, where the inductor current discharges to zero at
some point during the switching cycle. This causes the
AC component of the inductor current to be high com-
pared to the load current, which increases core losses
and I²R losses in the output filter capacitors. Obtain best
light-load efficiency by using MOSFETs with moderate
gate-charge levels and by using ferrite, MPP, or other
low-loss core material. Avoid powdered iron cores; even
Kool-mu (aluminum alloy) is not as good as ferrite.
__PC Board Layout Considerations
Good PC board layout is required to achieve specified
noise, efficiency, and stability performance. The PC
board layout artist must be provided with explicit
instructions, preferably a pencil sketch of the place-
ment of power switching components and high-current
routing. See the evaluation kit PC board layouts in the
MAX1653, MAX796, and MAX797 EV kit manuals for
examples. A ground plane is essential for optimum per-
formance. In most applications, the circuit will be locat-
ed on a multilayer board, and full use of the four or
more copper layers is recommended. Use the top layer
for high-current connections, the bottom layer for quiet
connections (REF, SS, GND), and the inner layers for
an uninterrupted ground plane. Use the following step-
by-step guide.
1) Place the high-power components (C1, C2, Q1, Q2,
D1, L1, and R1) first, with their grounds adjacent.
Priority 1: Minimize current-sense resistor trace
lengths (see Figure 9).
Priority 2: Minimize ground trace lengths in the
high-current paths (discussed below).
Priority 3:
Minimize other trace lengths in the high-
current paths. Use >5mm wide traces.
C1 to Q1: 10mm max length. D1 anode to
Q2: 5mm max length LX node (Q1
source, Q2 drain, D1 cathode, inductor):
15mm max length
Ideally, surface-mount power components are
butted up to one another with their ground terminals
almost touching. These high-current grounds (C1-,
C2-, source of Q2, anode of D1, and PGND) are
then connected to each other with a wide filled zone
24 ______________________________________________________________________________________