MAX1652 Datasheet, PDF (21/28 Pages) Maxim Integrated Products – High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP

High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
Input Capacitor Value
Place a small ceramic capacitor (0.1µF) between V+ and
GND, close to the device. Also, connect a low-ESR bulk
capacitor directly to the drain of the high-side MOSFET.
Select the bulk input filter capacitor according to input
ripple-current requirements and voltage rating, rather
than capacitor value. Electrolytic capacitors that have
low enough effective series resistance (ESR) to meet the
ripple-current requirement invariably have more than
adequate capacitance values. Ceramic capacitors or
low-ESR aluminum-electrolytic capacitors such as Sanyo
OS-CON or Nichicon PL are preferred. Tantalum types
are also acceptable but may be less tolerant of high
input surge currents. RMS input ripple current is deter-
mined by the input voltage and load current, with the
worst possible case occurring at V_IN = 2 x V_OUT:
I_RMS = I_LOAD x
V_{OUT (VIN − VOUT)}
V_IN
I_RMS = I_LOAD / 2 when V_IN is 2 x V_OUT
Output Filter Capacitor Value
The output filter capacitor values are determined by the
ESR, capacitance, and voltage rating requirements.
Electrolytic and tantalum capacitors are generally cho-
sen by voltage rating and ESR specifications, as they
will generally have more output capacitance than is
required for AC stability. Use only specialized low-ESR
capacitors intended for switching-regulator applications,
such as AVX TPS, Sprague 595D, Sanyo OS-CON, or
Nichicon PL series. To ensure stability, the capacitor
must meet both minimum capacitance and maximum
ESR values as given in the following equations:
V_REF (1 + V_OUT / V_IN(MIN))
C_OUT > ––––––––––––––––———–––
V_OUT x R_SENSE x f
R_SENSE x V_OUT
R_ESR < ————————
V_REF
(can be multiplied by 1.5, see note below)
These equations are “worst-case” with 45 degrees of
phase margin to ensure jitter-free fixed-frequency opera-
tion and provide a nicely damped output response for
zero to full-load step changes. Some cost-conscious
designers may wish to bend these rules by using less
expensive (lower quality) capacitors, particularly if the
load lacks large step changes. This practice is tolerable if
some bench testing over temperature is done to verify
acceptable noise and transient response.
There is no well-defined boundary between stable and
unstable operation. As phase margin is reduced, the
first symptom is a bit of timing jitter, which shows up as
blurred edges in the switching waveforms where the
scope won’t quite sync up. Technically speaking, this
(usually) harmless jitter is unstable operation, since the
switching frequency is now nonconstant. As the capac-
itor quality is reduced, the jitter becomes more pro-
nounced and the load-transient output voltage
waveform starts looking ragged at the edges.
Eventually, the load-transient waveform has enough
ringing on it that the peak noise levels exceed the
allowable output voltage tolerance. Note that even with
zero phase margin and gross instability present, the
output voltage noise never gets much worse than I_PEAK
x R_ESR (under constant loads, at least).
Note: Designers of RF communicators or other noise-
sensitive analog equipment should be conservative
and stick to the ESR guidelines. Designers of notebook
computers and similar commercial-temperature-range
digital systems can multiply the R_ESR value by a factor
of 1.5 without hurting stability or transient response.
The output voltage ripple is usually dominated by the
ESR of the filter capacitor and can be approximated as
I_RIPPLE x R_ESR. There is also a capacitive term, so the
full equation for ripple in the continuous mode is
V_NOISE(p-p) = I_RIPPLE x [R_ESR + 1 / (8 x f x C_OUT)]. In
Idle Mode, the inductor current becomes discontinuous
with high peaks and widely spaced pulses, so the noise
can actually be higher at light load compared to full load.
In Idle Mode, the output ripple can be calculated as:
0.025 x RESR
V_NOISE(p-p) = —————— +
R_SENSE
(0.025)² x L x [1 / V_OUT + 1 / (V_IN - V_OUT)]
———————————————————
(R_SENSE)² x C_OUT
Transformer Design
(MAX1652/MAX1654 Only)
Buck-plus-flyback applications, sometimes called “cou-
pled-inductor” topologies, use a transformer to generate
multiple output voltages. The basic electrical design is a
simple task of calculating turns ratios and adding the
power delivered to the secondary in order to calculate the
current-sense resistor and primary inductance. However,
extremes of low input-output differentials, widely different
output loading levels, and high turns ratios can compli-
cate the design due to parasitic transformer parameters
such as interwinding capacitance, secondary resistance,
and leakage inductance. For examples of what is possi-
ble with real-world transformers, see the graphs of
Maximum Secondary Current vs. Input Voltage in the
Typical Operating Characteristics.
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