MAX11902 Datasheet, PDF (24/29 Pages) Maxim Integrated Products – Fully Differential SAR ADC

MAX11902
18-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Conversion Result Register
An 18-bit read-only register, can be read directly or via a command read sequence.
Chip ID Register
This register holds a 4-bit code that can be used to verify the silicon revision. The ID = 1001b.
BIT 7
—
BIT 6
—
BIT 5
—
BIT 4
—
BIT 3
ID3
BIT 2
ID2
BIT 1
ID1
BIT 0
ID0
Typical Application Circuit
Real-world signals usually require conditioning before
they can be digitized by an ADC. The following outlines
common examples of analog signal processing circuits for
shifting, gaining, attenuating, and filtering signals.
Single-Ended Unipolar Input to Differential
Unipolar Output
The circuit in Figure 13 shows how a single-ended, uni-
polar signal can interface with the MAX11902. This signal
conditioning circuit transforms a 0V to +V_REF single-end-
ed input signal to a fully differential output signal with a
signal peak-to-peak amplitude of 2 x V_REF and common-
mode voltage (V_REF/2). In this case, the single-ended
signal source drives the high-impedance input of the first
amplifier. This amplifier drives the AIN+ input of ADC and
the second stage amplifier with peak-to-peak amplitude
of V_REF and common-mode output voltage of V_REF/2.
The second amplifier inverts this input signal and adds
an offset to generate an inverted signal with peak-to-peak
amplitude of V_REF and common-mode output voltage of
V_REF/2, which drives the AIN- input of ADC.
Single-Ended Bipolar Input to Differential
Unipolar Output
The MAX11902 is a differential input ADC that accepts
a differential input signal with unipolar common mode.
Figure 14 shows a signal conditioning circuit that trans-
forms a -2 x V_REF to +2 x V_REF single-ended bipolar
input signal to a fully differential output signal with ampli-
tude peak-to-peak 2 x V_REF and common-mode voltage
V_REF/2.
The single-ended bipolar input signal drives the inverting
input of the first amplifier. This amplifier inverts and adds
an offset to the input signal. It also drives the AIN- input
of ADC and the second stage amplifier with peak-to-peak
amplitude of V_REF and common-mode output voltage of
V_REF/2. The second amplifier is also in inverting configu-
ration and drives the AIN+ input of the ADC. This ampli-
fier adds an offset to generate a signal with peak-to-peak
amplitude of V_REF and common-mode output voltage
of V_REF/2. The input impedance, seen by the signal
source, depends on the input resistor of the first-stage
inverting amplifier. Input impedance must be chosen care-
fully based on the output source impedance of the signal
source.
Layout, Grounding, and Bypassing
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines paral-
lel to one another (especially clock lines), and avoid run-
ning digital lines underneath the ADC package. A single
solid GND plane configuration with digital signals routed
from one direction and analog signals from the other pro-
vides the best performance. Connect the GND pin on the
MAX11902 to this ground plane. Keep the ground return
to the power supply for this ground low impedance and as
short as possible for noise-free operation.
A 2nF C0G ceramic chip capacitor should be placed
between AIN+ and AIN- as close as possible to the
MAX11902. This capacitor reduces the voltage transient
seen by the input source circuit.
For best performance, connect the REF output to the
ground plane with a 16V, 10µF ceramic chip capacitor
with a X5R dielectric in a 1210 or smaller case size.
Ensure that all bypass capacitors are connected directly
into the ground plane with an independent via.
Bypass AVDD, DVDD, and OVDD to the ground plane with
10µF ceramic chip capacitors on each pin as close as pos-
sible to the device to minimize parasitic inductance. For
best performance, bring the AVDD and DVDD power plane
in from the analog interface side of the MAX11902 and the
OVDD power plane from the digital interface side of the
device. Figure 15 shows the top layer of a sample layout.
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