MAX11902 Datasheet, PDF (16/29 Pages) Maxim Integrated Products – Fully Differential SAR ADC

MAX11902
18-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Input Settling
During track phase (Figure 3), the sample switches are
closed and the analog inputs are directly connected to the
sample capacitors. The charging of the sample capacitor
to the input voltage is determined by the source resis-
tance and sampling capacitor size. The rising edge of
CNVST is the sampling instant for the ADC. At this instant,
the track phase ends, the sample switch opens, and the
device enters into the successive approximation (SAR)
conversion phase. In the conversion phase, a differential
comparator compares the voltage on the sample capaci-
tor against the CDAC value, which cycles through values
between V_REF/2 and V_REF/2²⁰ using the successive
approximation technique. The final result can be read via
the SPI bus. The ADC automatically goes back into track
phase at the end of SAR conversion and powers down its
active circuits. That is, the ADC consumes no static power
in track mode.
The conversion results will be accurate if the ADC tracks
the input signal for an interval longer than the input sig-
nal’s settling time. If the signal cannot settle within the
track time due to excessive source resistance, external
ADC drivers are required to achieve faster settling. Since
the MAX11902 has a fixed conversion time set by an
internal oscillator, track time can be increased by lowering
the sample rate for better settling.
The settling behavior is determined by the time constant
in the sampling network. The time constant depends upon
the total resistance (source resistance + switch resis-
tance) and total capacitance (sampling capacitor, external
input capacitor, PCB parasitic capacitors).
Modeling the input circuit with a single pole network, the
time constant, R_TOTAL × C_LOAD, of the input should not
exceed t_TRACK/15, where R_TOTAL is the total resistance
(source resistance + switch resistance), C_LOAD is the
total capacitance (sampling capacitor, external input
capacitor, PCB parasitic capacitor), and t_TRACK is the
track time.
When an ADC driver is used, it is recommended to use
a series resistance (typically 5Ω to 50Ω) between the
amplifier and the ADC input, as shown in the Application
Diagram. Below are some of the requirements for the
ADC driver amplifier:
1) Fast settling time: For a multichannel multiplexed cir-
cuit the ADC driver amplifier must be able to settle with
an error less than 0.5 LSB during the minimum track
time when a full-scale step is applied.
2) Low noise: It is important to ensure that the ADC driver
has a sufficiently low-noise density in the bandwidth
of interest of the application. When the MAX11902 is
used with its full bandwidth of 20MHz, it is preferable
to use an amplifier with an output noise spectral den-
sity of less than 3nV/√Hz, to ensure that the overall
SNR is not degraded significantly. It is recommended
to insert an external RC filter at the ADC input to
attenuate out-of-band input noise.
3) To take full advantage of the ADC’s excellent dynamic
performance, Maxim recommends the use of an ADC
driver with equal or even better THD performance.
This will ensure that the ADC driver does not limit
distortion performance in the signal path. Table 1 sum-
marizes the most important features of the MAX9632
when used as an ADC driver.
Input Filtering
Noisy input signals should be filtered prior to the ADC
driver amplifier input with an appropriate filter to minimize
noise. The RC network shown in the Application Diagram
is mainly designed to reduce the load transient seen by
the amplifier when the ADC starts the track phase. This
network also has to satisfy the settling time requirement
and provides the benefit of limiting the noise bandwidth.
Table 1. ADC Driver Amplifier Recommendation
AMPLIFIER
MAX9632
INPUT-NOISE
DENSITY (nV/√Hz)
1
SMALL-SIGNAL
BANDWIDTH (MHz)
55
SLEW RATE
(V/µs)
30
THD
(dB)
-128
I_CC
(mA)
3.9mA
COMMENTS
Low noise, THD at 10kHz
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