MAX11902 Datasheet, PDF (14/29 Pages) Maxim Integrated Products – Fully Differential SAR ADC

MAX11902
18-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Detailed Description
The MAX11902 is an 18-bit, 1Msps maximum sampling
rate, fully differential input, single-channel SAR ADC with
SPI interface. This part features industry-leading sample
rate and resolution, while consuming very low power. The
MAX11902 has an integrated reference buffer to minimize
board space, component count, and system cost. An
internal oscillator drives the conversion and sets conver-
sion time, easing external timing considerations.
Analog Inputs
Both analog inputs, AIN+ and AIN-, range from 0V to
V_REF. Thus, the differential input interval V_DIFF = (AIN+)
- (AIN-) ranges from -V_REF to +V_REF, and the full-scale
range is:
FSR = 2 x V_REF
The nominal resolution step width of the least significant
bit (LSB) is:
= LSB ^F= _2SN^R,N 18
The differential analog input must be centered around
a signal common mode of V_REF/2, with a tolerance of
±100mV.
The reference voltage can range from 2.5V to the refer-
ence supply, REFVDD, if an external reference buffer
is used. When using the on-board reference buffer the
reference voltage can range from 2.5V to 200mV below
reference supply REFVDD. This will guarantee adequate
headroom for the internal reference buffers.
Figure 1 illustrates signal ranges for AIN+/AIN-, reference
voltage V_REF and reference supply voltage REFVDD.
Figure 2 shows the input equivalent circuit of MAX11902.
The ADC samples both inputs, AIN+ and AIN-, with a fully
differential on-chip track-and-hold exhibiting no pipeline
delay or latency.
The MAX11902 has dedicated input clamps to protect
the inputs from overranging. Diodes D1 and D2 provide
ESD protection and act as a clamp for the input voltages.
Diodes D1/D2 can sustain a maximum forward current
of 100mA. The sampling switches connect inputs to the
sampling capacitors.
Figure 3 shows the timing of the digitizing cycle: Conversion
frame, SAR conversion, Track and Read operations.
V
REFVDD
V_REF
AIN+
0.5 x V_REF
AIN-
0V
Figure 1. Signal Ranges
200mV
V_REF +200mV ≤ V_REFVDD ≤ 3.6V
IF BUFFER IS ENABLED
V_REF ≤ V_REFVDD ≤ 3.6V
IF BUFFER IS DISABLED
time
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