MAX11044_11 Datasheet, PDF (23/27 Pages) Maxim Integrated Products – 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Layout, Grounding, and Bypassing
For best performance use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines paral-
lel to one another (especially clock lines), and avoid run-
ning digital lines underneath the ADC package. A single
solid GND plane configuration with digital signals routed
from one direction and analog signals from the other pro-
vides the best performance. Connect DGND, AGND, and
AGNDS pins on the MAX11044/MAX11045/MAX11046
and MAX11054/MAX11055/MAX11056 to this ground
plane. Keep the ground return to the power supply for this
ground low impedance and as short as possible for noise-
free operation.
To achieve the highest performance, connect all the
RDC pins (22, 28, 35, 43, 49 for the TQFN package, or
pins 27, 33, 40, 48, 54 for the TQFP package) to a local
RDC plane on the PCB. In addition, on the TQFP pack-
age, the RDC_SENSE pins 26 and 55 should be directly
connected to this RDC plane as well. Bypass the RDC
outputs with a total of at least 80µF of capacitance. If
two capacitors are used, place each as close as possi-
ble to pins 22 and 49 (TQFN) or pins 27 and 54 (TQFP).
If four capacitors are used, place each as close as pos-
sible to pins 22, 28, 43, and 49 (TQFN) or pins 27, 33,
48, and 54 (TQFP). For example, two 47µF, 10V X5R
capacitors in 1210 case size can be placed as close as
possible to pins 22 and 49 (TQFN package) will provide
excellent performance. Alternatively, four 22µF, 10V
X5R capacitors in 1210 case size placed as close as
possible to pins 22, 28, 43, and 49 (TQFN package) will
also provide good performance. Ensure that each
capacitor is connected directly into the GND plane with
an independent via.
If Y5U or Z5U ceramics are used, be aware of the high-
voltage coefficient these capacitors exhibit and select
higher voltage rating capacitors to ensure that at least
80µF of capacitance is on the RDC plane when the
plane is driven to 4.096V by the built-in reference
buffer. For example, a 22µF X5R with a 10V rating is
approximately 20µF at 4.096V, whereas, the same
capacitor in Y5U ceramic is just 13µF. However, a Y5U
22µF capacitor with a 25V rating cap is approximately
20µF at 4.096V.
Bypass AVDD and DVDD to the ground plane with
0.1µF ceramic chip capacitors on each pin as close as
possible to the device to minimize parasitic inductance.
Add at least one bulk 10µF decoupling capacitor to
AVDD and DVDD per PCB. Interconnect all of the
AVDD inputs and DVDD inputs using two solid power
planes. For best performance, bring the AVDD power
plane in on the analog interface side of the MAX11044/
MAX11045/MAX11046 and MAX11054/MAX11055/
MAX11056 and the DVDD power plane from the digital
interface side of the device.
For acquisition periods near minimum (1µs) use a 1nF
C0G ceramic chip capacitor between each of the chan-
nel inputs to the ground plane as close as possible to
the MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056. This capacitor reduces the
inductance seen by the sampling circuitry and reduces
the voltage transient seen by the input source circuit.
Typical Application Circuits
Power-Grid Protection
Figure 10 shows a typical power-grid protection application.
DSP Motor Control
Figure 11 shows a typical DSP motor control application.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For these devices, this
straight line is a line drawn between the end points of
the transfer function, once offset and gain errors have
been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. For these devices, the DNL of
each digital output code is measured and the worst-case
value is reported in the Electrical Characteristics table. A
DNL error specification of greater than -1 LSB guaran-
tees no missing codes and a monotonic transfer func-
tion. For example, -0.9 LSB guarantees no missing code
while -1.1 LSB results in missing code.
Offset Error
The offset error is defined as the input voltage required
to cause the MAX11044/MAX11045/MAX11046 digital
output to be centered on code 0X8000 (offset binary) or
0x0000 (two’s complement) and the MAX11054/
MAX11055/MAX11056 digital output to be centered on
code 0X2000 (offset binary) or 0x0000 (two’s comple-
ment). Ideally, this input voltage should be 0V with
respect to GND.
Gain Error
Gain error is defined as the difference between the
change in analog input voltage required to produce a top
code transition minus a bottom code transition, subtract-
ed from the ideal change in analog input voltage on
(10/4.096) x V_REF x (65,534/65,536) for 16-bit, or
(10/4.096) x V_REF x (16,382/16,384) for 14-bit devices.
For the MAX11044/MAX11045/MAX11046, top code tran-
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