MAX11044_11 Datasheet, PDF (16/27 Pages) Maxim Integrated Products – 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
is driven by an internal bandgap reference circuit (V_RE-
FIO ^{= 4.096V). Drive REFIO with an external reference or}
bypass with 0.1µF capacitor to ground when using the
internal reference.
Analog Inputs
Track and Hold (T/H)
To preserve phase information across all channels,
each input includes a dedicated T/H circuitry. The input
tracking circuitry provides a 4MHz small-signal band-
width, enabling the device to digitize high-speed tran-
sient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Use anti-alias filtering
to avoid high-frequency signals being aliased into the
frequency band of interest.
Input Range and Protection
The full-scale analog input voltage is a product of the ref-
erence voltage. For the MAX11044/MAX11045/
MAX11046 and MAX11054/MAX11055/MAX11056, the
full-scale input is bipolar in the range of:
±(V_REFIO
x
5)
4.096
When in external reference mode, drive V_REFIO with a
3.0V to 4.25V source, resulting in an input range of
±3.662V to ±5.188V, respectively.
All analog inputs are fault-protected to up to ±20mA.
The MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056 include an input clamping circuit
that activates when the input voltage at the analog input
is above (V_AVDD + 300mV) or below –(V_AVDD + 300mV).
The clamp circuit remains high impedance while the
input signal is within the range of ±V_AVDD and draws lit-
tle or almost no current. However, when the input signal
exceeds ±V_AVDD, the clamps begin to turn on and
shunt current to/from the AVDD supply. Consequently,
to obtain the highest accuracy, ensure that the input
voltage does not exceed ±(V_AVDD + 0.3V).
To make use of the input clamps (see Figure 1), con-
nect a resistor (R_S) between the analog input and the
voltage source to limit the voltage at the analog input so
that the fault current into the MAX11044/MAX11045/
MAX11046 and MAX11054/MAX11055/MAX11056 does
not exceed ±20mA. Note that the voltage at the analog
input pin limits to approximately 7V during a fault condi-
tion so the following equation can be used to calculate
the value of R_S:
INPUT
SIGNAL
PIN
VOLTAGE
AVDD
R_S
CH0
CLAMP S/H
16-/14-BIT ADC
DVDD
DB15**
SOURCE
CH7^†
CLAMP S/H
16-/14-BIT ADC
DB4
DB3/CR3
DB0/CR0
AGNDS
AGND
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
INT REF
10kΩ
BANDGAP
REF
REFERENCE
BUF
REFIO
EXT REF
CONFIGURATION
REGISTERS
INTERFACE
AND
CONTROL
WR
RD
CS
CONVST
SHDN
EOC
DGND
RDC
RDC_SENSE*
*CONNECTED INTERNALLY ON THE TQFN PARTS TO RDC
**MAX11044/MAX11045/MAX11046
†_{MAX11046/MAX11056}
Figure 1. Required Setup for Clamp Circuit
16 ______________________________________________________________________