MAX11044_11 Datasheet, PDF (12/27 Pages) Maxim Integrated Products – 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description (continued)
MAX11044
(TQFP-EP)
1
2
3
4
5
6
7
8, 22, 59
9, 21, 60
10
11
12
13
14
15
16
17
18
PIN
MAX11045
(TQFP-EP)
1
2
3
4
5
6
7
8, 22, 59
9, 21, 60
10
11
12
13
14
15
16
17
18
MAX11046
(TQFP-EP)
1
2
3
4
5
6
7
8, 22, 59
9, 21, 60
10
11
12
13
14
15
16
17
18
19
19
19
20
20
20
23, 28, 32, 38,
43, 49, 53, 58
24, 29, 35, 46,
52, 57
25, 30, 36, 45,
51, 56
23, 28, 32, 38,
43, 49, 53, 58
24, 29, 35, 46,
52, 57
25, 30, 36, 45,
51, 56
23, 28, 32, 38,
43, 49, 53, 58
24, 29, 35, 46,
52, 57
25, 30, 36, 45,
51, 56
NAME
FUNCTION
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DGND
DVDD
DB7
DB6
DB5
DB4
DB3/CR3
DB2/CR2
DB1/CR1
DB0/CR0
EOC
CONVST
SHDN
AGNDS
AVDD
AGND
16-Bit Parallel Data Bus Digital Output Bit 14
16-Bit Parallel Data Bus Digital Output Bit 13
16-Bit Parallel Data Bus Digital Output Bit 12
16-Bit Parallel Data Bus Digital Output Bit 11
16-Bit Parallel Data Bus Digital Output Bit 10
16-Bit Parallel Data Bus Digital Output Bit 9
16-Bit Parallel Data Bus Digital Output Bit 8
Digital Ground
Digital Supply. Bypass to DGND with a 0.1µF capacitor
at each DVDD input.
16-Bit Parallel Data Bus Digital Output Bit 7
16-Bit Parallel Data Bus Digital Output Bit 6
16-Bit Parallel Data Bus Digital Output Bit 5
16-Bit Parallel Data Bus Digital Output Bit 4
16-Bit Parallel Data Bus Digital Output Bit 3/
Configuration Register Input Bit 3
16-Bit Parallel Data Bus Digital Output Bit 2/
Configuration Register Input Bit 2
16-Bit Parallel Data Bus Digital Output Bit 1/
Configuration Register Input Bit 1
16-Bit Parallel Data Bus Digital Output Bit 0/
Configuration Register Input Bit 0
Active-Low End-of-Conversion Output. EOC goes low
when conversion is completed. EOC goes high when a
conversion is initiated.
Convert Start Input. Rising edge of CONVST ends
sample and starts a conversion on the captured sample.
The ADC is in acquisition mode when CONVST is low
and CONVST mode = 0.
Shutdown Input. If SHDN is held high, the entire device
will enter and stay in a low-current state. Contents of
the configuration register are not lost when in the
shutdown mode.
Signal Ground. Connect all AGND and AGNDS inputs
together on PWB.
Analog Supply Input. Bypass AVDD to AGND with a
0.1µF capacitor at each AVDD input.
Analog Ground. Connect all AGND inputs together.
12 ______________________________________________________________________________________