MAX106CHC-D Datasheet, PDF (23/31 Pages) Maxim Integrated Products – ±5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier

±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
ADC SAMPLE NUMBER
CLK- n
n+1
n+2
n+3
CLK
CLK+
RESET
INPUT
t_SU
RSTIN-
RSTIN+
DREADY+
DREADY
DREADY-
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
RESET OUT
DATA PORT
RSTOUT-
RSTOUT+
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+4
n+5
n+6
n+7
n+8
t_HD
n-2
n-1
n+9 n+10 n+11 n+12 n+13
CLOCK PULSE “SWALLOWED”
OUT-OF-SEQUENCE SAMPLE
n
n+2
n+1
n+4
NOTE: DREADY PHASE WAS ADJUSTED TO MATCH THE RESET PHASE BY “SWALLOWING” ONE INPUT CLOCK CYCLE.
THE AUXILIARY PORT CONTAINS AN OUT-OF-SEQUENCE SAMPLE AS A RESULT OF THE DELAY.
Figure 19. Reset Output Timing in Demuxed DIV2 Mode (DREADY Realigned)
asserted, the auxiliary port contained “even” samples
while the primary port contained “odd” samples. After
RSTOUT is deasserted (which marks the start of the
DREADY clock’s reset phase), note that the order of the
samples in the ports has been reversed. The auxiliary
port also contains an out-of-sequence sample. This is a
consequence of the “swallowed” clock cycle that was
needed to resynchronize DREADY to the reset phase.
Also note that the older sample data is always in the aux-
iliary port, regardless of the DREADY phase.
These examples show the combinations that result with
a reset input signal of two clock cycles. It is also possi-
ble to successfully reset the internal MAX106 demux
with a reset pulse only one clock cycle long, proving
the setup-time and hold-time requirements are met with
respect to the sample clock. However, this is not rec-
ommended when additional external demuxes are
used.
Note that many external demuxes require their reset
signals to be asserted while they are clocked, and may
require more than one clock cycle of reset. More impor-
tantly, if the phase of the DREADY clock is such that a
clock pulse will be “swallowed” to resynchronize, then
no reset output will occur at all. In effect, the RSTOUT
signal will be “swallowed” along with the clock pulse.
The best method to ensure complete system reset is to
assert RSTIN for the appropriate number of DREADY
clock cycles required to complete reset of the external
demuxes.
Die Temperature Measurement
For applications that require monitoring of the die tem-
perature, it is possible to determine the die temperature
of the MAX106 under normal operating conditions by
observing the currents I_CONST and I_PTAT, at contacts
ICONST and IPTAT. I_CONST and I_PTAT are two 100µA
(nominal) currents that are designed to be equal at
+27°C. These currents are derived from the MAX106’s
internal precision +2.5V bandgap reference. I_CONST is
designed to be temperature independent, while I_PTAT is
directly proportional to the absolute temperature. These
currents are derived from pnp current sources refer-
enced from V_CCI and driven into two series diodes con-
nected to GNDI. The contacts ICONST and IPTAT may
be left open because internal catch diodes prevent sat-
uration of the current sources. The simplest method of
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