MAX106CHC-D Datasheet, PDF (20/31 Pages) Maxim Integrated Products – ±5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier

±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Table 5. DC-Coupled Clock Drive Options
CLOCK DRIVE
Single-Ended Sine Wave
Differential Sine Wave
Single-Ended ECL
Differential ECL
CLK+
-10dBm to +4dBm
-10dBm to +4dBm
ECL Drive
ECL Drive
CLK-
External 50Ω to GNDI
-10dBm to +4dBm
-1.3V
ECL Drive
CLKCOM
GNDI
GNDI
-2V
-2V
REFERENCE
Figure 13a
Figure 13b
Figure 13c
Figure 13d
AC-Coupling Clock Inputs
The clock inputs CLK+ and CLK- can also be driven
with positive referenced ECL (PECL) logic levels if the
V_CCO
clock inputs are AC-coupled. Under this condition, con-
nect CLKCOM to GNDI. Single-ended ECL/PECL/sine-
wave drive is also possible if the undriven clock input is
reverse-terminated to GNDI through a 50Ω resistor in
series with a capacitor whose value is identical to that
50k
50k
used to couple the driven input.
RSTIN+
Demux Reset Operation
The MAX106 features an internal 1:2 demultiplexer that
reduces the data rate of the output digital data to one-
RSTIN-
half the sample clock rate. Demux reset is necessary
when interleaving multiple MAX106s and/or synchroniz-
ing external demultiplexers. The simplified block dia-
20µA
gram of Figure 1 shows that the demux reset signal path
consists of four main circuit blocks. From input to out-
put, they are the reset input dual latch, the reset
pipeline, the demux clock generator, and the reset out-
put. The signals associated with the demux reset opera-
GNDD
tion and the control of this section are listed in Table 6.
RESET INPUTS ARE ESD PROTECTED
Reset Input Dual Latch
(NOT SHOWN ON THIS SIMPLIFIED DRAWING).
The reset input dual-latch circuit block accepts differ-
ential PECL reset inputs referenced to the same V_CCO
power supply that powers the MAX106 PECL outputs.
Figure 14. Simplified Reset Input Structure
For applications that do not require a synchronizing
reset, the reset inputs can be left open. In this case,
they will self-bias to a proper level with internal 50kΩ
RSTIN+
resistors and a 20µA current source. This combination
creates a -1V difference between RSTIN+ and RSTIN-
to disable the internal reset circuitry. When driven with
50%
50%
RSTIN-
PECL logic levels terminated with 50Ω to (V_CCO - 2V),
the internal biasing network can easily be overdriven.
t_SU
t_HD
Figure 14 shows a simplified schematic of the reset
input structure.
CLK+
To properly latch the reset input data, setup (t_SU) and
data-hold times (t_HD) must be met with respect to the
50%
CLK-
rising edge of the sample clock. The timing diagram of
Figure 15 shows the timing relationship of the reset
input and sampling clock.
Figure 15. Reset Input Timing Definitions
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