MAX1221 Datasheet, PDF (22/44 Pages) Maxim Integrated Products – 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
LSB per degree. See the Temperature Measurements
section for details on converting the digital code to a tem-
perature.
12-Bit DAC
In addition to the 12-bit ADC, the MAX1221/MAX1223/
MAX1343 also include eight (MAX1221/MAX1223) or
four (MAX1343) voltage-output, 12-bit, monotonic DACs
with less than 4 LSB integral nonlinearity error and less
than 1 LSB differential nonlinearity error. Each DAC has
a 2µs settling time and ultra-low glitch energy (4nV•s).
The 12-bit DAC code is unipolar binary with 1 LSB =
V_REF / 4096.
DAC Digital Interface
Figure 1 shows the functional diagram of the MAX1221.
The shift register converts a serial 16-bit word to parallel
data for each input register operating with a clock rate
up to 25MHz. The SPI-compatible digital interface to the
shift register consists of CS, SCLK, DIN, and DOUT.
Serial data at DIN is loaded on the falling edge of SCLK.
Pull CS low to begin a write sequence. Begin a write to
the DAC by writing 0001XXXX as a command byte. The
last 4 bits of the DAC select register are don’t-care bits.
See Table 10. Write another 2 bytes to the DAC inter-
face register following the command byte to select the
appropriate DAC and the data to be written to it. See
Tables 17 and 18.
The double-buffered DACs include an input and a DAC
register. The input registers are directly connected to the
shift register and hold the result of the most recent write
operation. The 12-bit DAC registers hold the current out-
put code for the respective DAC. Data can be transferred
from the input registers to the DAC registers by pulling
LDAC low or by writing the appropriate DAC command
sequence at DIN. See Table 17. The outputs of the DACs
are buffered through eight (MAX1221/MAX1223) or four
(MAX1343) rail-to-rail op amps.
The MAX1221/MAX1223/MAX1343 DAC output-voltage
range is based on the internal reference or an external
reference. Write to the setup register (see Table 5) to
program the reference. If using an external voltage
reference, bypass REF1 with a 0.1µF capacitor to
AGND. The internal reference is 2.5V. When using an
external reference on any of these devices, the voltage
range is 0.7V to AV_DD.
DAC Transfer Function
See Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up Modes
The state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AV_DD or
AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩ internal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AV_DD to wake up all DAC outputs
at FFFh. While RES_SEL is high, the 100kΩ pullup
resistor pulls the DAC outputs to V_REF1 and the output
buffers are powered down.
DAC Power-Up Modes
See Table 18 for a description of the DAC power-up
and power-down modes.
GPIOs
In addition to the internal ADC and DAC, the
MAX1221/MAX1343 also provide four GPIO channels,
GPIOA0, GPIOA1, GPIOC0, GPIOC1. Read and write to
the GPIOs as detailed in Table 1 and Tables 12–16. Also,
see the GPIO Command section. See Figures 11 and 12
for GPIO timing.
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1221/MAX1343 following the command byte.
The GPIOs can sink and source current. GPIOA0 and
GPIOA1 can sink and source up to 15mA. GPIOC0 and
GPIOC1 can sink 4mA and source 2mA. See Table 3.
Table 2. DAC Output Code Table
DAC CONTENTS
MSB
LSB
ANALOG OUTPUT
1111 1111 1111
+V_REF
⎛ 4095⎞
⎝⎜ 4096⎠⎟
1000 0000 0001
+V_REF
⎛
⎝⎜
2049 ⎞
4096 ⎠⎟
1000
0000
0000
+V_REF
⎛ 2048 ⎞
⎝⎜ 4096⎠⎟
=
⎛
⎝⎜
+V_REF
2
⎞
⎠⎟
0111 0111 0111
+V_REF
⎛ 2047 ⎞
⎝⎜ 4096⎠⎟
0000 0000 0001
0000 0000 0000
+V_REF
⎛
⎝⎜
1⎞
4096 ⎠⎟
0
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