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MAX1221 Datasheet, PDF (16/44 Pages) Maxim Integrated Products – 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Description
MAX1221
1, 2
PIN
MAX1223
—
MAX1343
1, 2
NAME
GPIOA0, GPIOA1
FUNCTION
General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.
—
1
—
CNVST/AIN11 Active-Low Conversion-Start Input/Analog Input 11. See Table 5 for details
on programming the setup register.
3
3
3
EOC
Active-Low End-of-Conversion Output. Data is valid after the falling edge
of EOC.
4
4
4
5
5
5
DVDD
DGND
Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF
capacitor.
Digital Ground. Connect DGND to AGND.
6
6
6
DOUT
Serial-Data Output. Data is clocked out on the falling edge of the SCLK
clock in modes 00, 01, and 10. Data is clocked out on the rising edge of
the SCLK clock in mode 11. It is high impedance when CS is high.
7
8
—
9–12,
16–19
13
14
15, 23,
32, 33
—
20
21
22
24, 25
7
8
—
9–12,
16–19
13
14
2, 15, 24,
32
—
20
21
22
—
7
8
9–12
—
13
14
15, 23,
32, 33
16–19
20
21
22
24, 25
SCLK
DIN
OUT0–OUT3
OUT0–OUT7
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty
cycle must be 40% to 60%). See Table 5 for details on programming the
clock mode.
Serial-Data Input. DIN data is latched into the serial interface on the falling
edge of SCLK.
DAC Outputs
DAC Outputs
AVDD
AGND
N.C.
Positive Analog Power Input. Bypass AVDD to AGND with a 0.1µF
capacitor.
Analog Ground
No Connection. Not internally connected.
D.C.
LDAC
Do Not Connect. Do not connect to this pin.
Active-Low Load DAC. LDAC is an asynchronous active-low input that
updates the DAC outputs. Drive LDAC low to make the DAC registers
transparent.
CS
Active-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
RES_SEL
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up
the DAC outputs with a 100kΩ resistor to GND or set RES_SEL high to
wake up the DAC outputs with a 100kΩ resistor to VREF. The default is the
external VREF.
GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, C1 can sink 4mA and source 2mA.
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