DS3100 Datasheet, PDF (210/226 Pages) Maxim Integrated Products – Stratum 3/3E Timing Card IC

DS3100 Stratum 3/3E Timing Card IC
10.5 Parallel Interface Timing
Table 10-13. Parallel Interface Timing
(V_DD = 1.8V ±10%, V_DDIO = 3.3V ±5%, T_A = -40°C to +85°C.) (Note 1) (See Figure 10-6 and Figure 10-7.)
PARAMETER
SYMBOL CONDITIONS MIN TYP MAX UNITS
Address Setup to RD, WR, DS Active
t1a (Note 2)
10
ns
ALE Setup to RD, WR, DS Active
t1b (Notes 2, 3)
10
ns
Address Setup to ALE Inactive
t2
(Notes 2, 3)
2
ns
Address Hold from ALE Inactive
t3
(Notes 2, 3)
2
ns
ALE Pulse Width
t4
(Notes 2, 3)
5
ns
Address Hold from RD, WR, DS Inactive
t5
(Note 2)
0
ns
CS Setup to RD, WR, DS Active
t6
(Note 2)
0
ns
Data Valid from RD, DS Active
t8
(Note 2)
80
ns
RD, WR, DS Pulse Width if not Using RDY
Handshake
t9a (Notes 2, 4)
90
ns
RD, WR, DS Delay from RDY Active
t9b (Note 2)
15
ns
Data Output High Impedance from RD, DS
Inactive
t10
(Notes 2, 5)
2
10
ns
Data Output Enabled from RD, DS Active
t11 (Note 2)
2
ns
CS Hold from RD, WR, DS Inactive
t12 (Note 2)
0
ns
Data Setup to WR, DS Inactive
t13 (Note 2)
10
ns
Data Hold from WR, DS inactive
t14 (Note 2)
5
ns
RDY Active from RD, WR, DS Active
t15 (Note 2)
10
ns
RDY Inactive from RD, WR, DS Inactive
t16 (Note 2)
0
10
ns
RDY Output Enabled from CS Active
t17 (Note 2)
10
ns
RDY Output High Impedance from CS
Inactive
t18 (Note 2)
10
ns
RDY Ending High Pulse Width
t19 (Note 2)
2
ns
R/W Setup to DS Active
t20 (Note 2)
2
ns
R/W Hold from DS Inactive
t21 (Note 2)
2
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
The timing parameters in this table are guaranteed by design (GBD).
The input/output timing reference level for all signals is VDD/2. Transition time (80/20%) on RD, WR, and CS inputs is 5ns max.
Multiplexed mode timing only.
Timing required if not using RDY handshake.
D[7:0] output valid until not driven.
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