DS3100 Datasheet, PDF (182/226 Pages) Maxim Integrated Products – Stratum 3/3E Timing Card IC

DS3100 Stratum 3/3E Timing Card IC
Register Name:
Register Description:
Register Address:
BRBCR
BITS Receive BOC Control Register (DS1 only)
40h
Name
Default
Bit 7
RBR
0
Bit 6
—
0
Bit 5
Bit 4
RBD[1:0]
0
0
Bit 3
0
Bit 2
RBF[2:0]
0
Bit 1
0
Bit 0
—
0
When the BITS receive framer is in DS1 ESF mode this register configures the receive BOC controller. In E1 mode
this register is reserved and should not be written. See Section 7.10.5.3.
Bit 7: Receive BOC Reset (RBR). A zero-to-one transition resets the BOC circuitry. RBR must be cleared and set
again for a subsequent reset. Modifications to the RBF and RBD fields are not applied to the BOC controller until a
BOC reset has been completed.
Bits 5 to 4: Receive BOC Disintegration Bits (RBD[1:0]). The receive BOC logic must examine the number of
message bits specified by RBD[1:0] before declaring that a valid BOC is no longer detected. The BC bit in BRSR4
is set to indicate that a valid BOC is no longer present.
RBD[1:0]
00
01
10
11
Consecutive Message Bits for BOC Clear
16
32
48
64
Bits 3 to 1: Receive BOC Filter Bits (RBF[2:0]). The receive BOC logic uses the criteria specified by this field to
validate incoming BOC codes. The BD bit in BRSR4 is set to indicate the detection of a validated BOC code.
RBF[2:0]
000
001
010
011
100
Validation Criteria for BOC Detected
1
3 in a row
5 in a row
7 in a row
7 out of 10
Register Name:
Register Description:
Register Address:
BTBCR
BITS Transmit BOC Control Register (DS1 only)
41h
Name
Default
Bit 7
—
0
Bit 6
SBOC
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
—
0
Bit 1
—
0
Bit 0
—
0
When the BITS transmitter is in DS1 mode ESF mode this register configures the transmit BOC controller. In all
other modes this register is reserved and should not be written. See Section 7.10.5.3.
Bit 6: Send BOC (SBOC).
0 = Do not transmit BOC codes
1 = Repeatedly transmit the BOC code stored in the BTBOC register
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