MAX1363 Datasheet, PDF (20/24 Pages) Maxim Integrated Products – 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response

4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
Table 13. Readback-Mode Format
ALARM RESET/SCAN SPEED
AIN0
THRESHOLDS
AIN1 THRESHOLDS
(SKIP IF DIFFERENTIAL
MODE OR CS1, CS0 < 1)
AIN2 THRESHOLDS
(SKIP IF CS1, CS0 < 2)
1 1 1 1 D2 D1 D0 INT 24 bits
24 bits
24 bits
AIN3 THRESHOLDS
(SKIP IF DIFFERENTIAL
MODE OR CS1, CS0 < 3)
24 bits
Table 14. Reading in Monitor-Mode Data Format
ALARM-STATUS REGISTER
8 bits
LATCHED-FAULT REGISTER
16, 32, 48, or 64 bits
CURRENT-CONVERSION RESULTS
16, 32, 48, or 64 bits
Table 15. Alarm-Status Register
CH0 UP
CH0 LOW
0/1
0/1
0 = Not-alarm condition.
1 = Alarm condition.
CH1 UP
0/1
CH1 LOW
0/1
Table 16. Latched-Fault and Current-
Conversion Register
AIN0
16-bit read
AIN1
16-bit read
AIN2
16-bit read
AIN3
16-bit read
bipolar mode, or set the lower threshold to 0x000 and
the upper threshold to 0xFFF for unipolar mode.
Readback Mode
Select readback mode by setting CS3, CS2 to [1,1] in
the configuration byte. Begin a read operation to start
reading back monitor-setup data. Clock out delay bit
settings, INT_EN bit, and the lower and upper thresh-
olds programmed for each channel. Readback mode
follows exactly the same format as writing to the moni-
tor-setup data, with the exception of the first 4 alarm-
reset bits, which are always 1 (Table 13).
Reading in Monitor Mode
Reading in monitor mode reads back the alarm-status
register, latched-fault register, and current-conversion
results as shown in Table 14.
The MAX1363/MAX1364 register pointer loops back to
the beginning of the current-conversion result after
reading the last conversion result. Stop reading at any
time by asserting a STOP condition or NACK.
Note: The MAX1363/MAX1364 do not update the cur-
rent-conversion results register while reading in monitor
mode. Monitor mode resumes after a STOP condition or
NACK.
CH2 UP
0/1
CH2 LOW
0/1
CH3 UP
0/1
CH3 LOW
0/1
Alarm-Status Register and Latched-Fault Register
The latched-fault register records a snapshot of the
alarming channel at the instance that a fault condition is
asserted. An alarm-status bit of 1 (Table 15) indicates a
fault, and the data in the latched-fault register of the
corresponding channel contains the conversion result
that caused the alarm to trip. Resetting alarms does not
clear the latched-fault register, thus the latched-fault
register contains valid data only if an alarm status bit is
high for the given channel.
The current-conversion register contains the most
recent conversion results. If the user attempts to read
past the last result of the current-conversion register,
the MAX1363/MAX1364 wraps back to the beginning of
the current-conversion result.
The latched-fault register and current-conversion regis-
ter follow the data format in the Reading a Conversion
(Read Cycle) section. Register length depends on the
number of conversions in one monitoring sequence. For
example, when channel pairs 0/1 and channels 2/3 are
monitored differentially, there are only two conversion
results to report. The latched-fault register is 2 x 16 bits
long, after which two current-conversion results follow.
Likewise, if CS0 and CS1 limit the upper bound of the
channel scan range from CH0 to CH2 in single-ended
mode, the latched-fault register clocks out 3 x 16 bits of
data followed by the current-conversion results, also 3 x
16 bits.
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