MAX1363 Datasheet, PDF (19/24 Pages) Maxim Integrated Products – 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response

4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
Table 9. Monitor-Mode Setup Data Format
Alarm reset, scan
speed, INT_EN ,
(8 bits)
AIN0 thresholds
(24 bits)
AIN1 thresholds
(skip if differential mode, or
CS1, CS0 < 1) (24 bits)
AIN2 thresholds (skip if AIN3 thresholds (skip if differential
CS1, CS0 < 2)
mode, or CS1, CS0 < 3)
(24 bits)
(24 bits)
Table 10. Alarm Reset, Scan Speed Register, and INT_EN Data Format
RESET
RESET
RESET
RESET
ALARM CH 0 ALARM CH 1 ALARM CH 2 ALARM CH 3
DELAY 2
DELAY 1
DELAY 0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
INT_EN
0/1
Table 11. Delay Settings
DELAY 2 DELAY 1 DELAY 0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MONITOR-MODE
CONVERSION RATE
(ksps)
133.0*
66.5
33.3
16.6
8.3
4.2
2.0
1.0
*When using delay = [0,0,0] in internal reference mode and
AIN3/REF configured as a REF output, the MAX1363/MAX1364
may exhibit a code-dependent gain error due to insufficient
internal reference drive. Gain error caused by this phenomenon
is typically less than 1%FSR (0.1µF C_REF) and increases with a
larger C_REF. Avoid this gain error by using an external reference,
V_DD, as a reference or use an internal reference with AIN3/REF
as an analog input (see Table 4). Alternatively, choose delay bits
other than [0,0,0] to lower the conversion rate.
clearing all alarms or by initiating an SMBus alert dur-
ing an alarm condition (see the SMBus Alert section).
The Delay 2, Delay 1, Delay 0 bits set the speed of
monitoring by changing the delay between conver-
sions. Delay 2, 1, 0 = 000 sets the maximum possible
speed; 001 divides the maximum speed by ~2.
Increasing delay values further divides the previous
speed by two.
INT_EN controls the open-drain INT output. Set INT_EN
to 1 to enable the hardware interrupt. Set INT_EN to 0
to disable the hardware interrupt output. The INT output
tri-states when disabled or when there are no alarms.
The master can also poll the alarm status register at
any time to check the alarm status.
Repeat clocking channel threshold data up to the chan-
nel programmed by CS1 and CS0 (Table 12). For differ-
ential input mode, omit odd channels; the lower and
upper threshold data applies to channel pairs. There is
no need to clock in dummy data for odd (or even)
channels (Table 6).
To disable alarming on a specific channel, set the lower
threshold to 0x800 and the upper threshold to 0x7FF for
Table 12. Lower and Upper Threshold Data Format
BYTE
1
B7
LT11
(MSB)
2
LT3
3
UT7
X = Don’t care.
ACK = Acknowledge.
B6
LT10
LT2
UT6
B5
B4
B3
LT9
LT8
LT7
LT1
LT0 (LSB) ^UT11
(MSB)
UT5
UT4
UT3
B2
LT6
UT10
UT2
B1
B0
ACKNOWLEDGE
LT5
LT4
ACK
UT9
UT8
UT1 UT0 (LSB)
ACK
ACK
______________________________________________________________________________________ 19