MAX11102_12 Datasheet, PDF (20/30 Pages) Maxim Integrated Products – 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs

MAX11102/03/05/06/10/11/15/16/17
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Pin Configurations
TOP VIEW
+
AIN1 1
AIN2 2
AGND 3
REF 4
VDD 5
10 SCLK
MAX11102
MAX11103
MAX11106
MAX11111
EP*
9 DOUT
8 OVDD
7 CHSEL
6 CS
TOP VIEW
AIN1 1 ⁺
10 SCLK
AIN2 2
AGND 3
REF 4
MAX11102
MAX11103
9 DOUT
8 OVDD
7 CHSEL
VDD 5
EP* ^{6 CS}
µMAX
TOP VIEW
VDD 1 ⁺
GND 2
MAX11105
MAX11110
MAX11115
MAX11116
MAX11117
AIN 3
6 CS
5 DOUT
4 SCLK
SOT23
TDFN
*CONNECT EXPOSED PAD TO GROUND PLANE. DEVICES DO NOT OPERATE WHEN EP IS NOT CONNECTED TO GROUND!
TDFN
1
2
—
—
3
4
5
6
7
8
9
10
—
20  
Pin Description
PIN
µMAX
1
2
—
—
3
4
5
6
7
8
9
10
—
SOT23
—
—
3
2
—
—
NAME
AIN1
AIN2
AIN
GND
AGND
REF
FUNCTION
Analog Input Channel 1. Single-ended analog input with respect to AGND with range
of 0V to VREF.
Analog Input Channel 2. Single-ended analog input with respect to AGND with range
of 0V to VREF.
Analog Input Channel. Single-ended analog input with respect to GND with range of
0V to VDD.
Ground. Connect GND to the GND ground plane.
Analog Ground. Connect AGND directly the GND ground plane.
External Reference Input. REF defines the signal range of the input signal AIN1/AIN2:
0V to VREF. The range of VREF is 1V to VDD. Bypass REF to AGND with 10FF || 0.1FF
capacitor.
Positive Supply Voltage. Bypass VDD with a 10FF || 0.1FF capacitor to GND. VDD
1
VDD range is 2.2V to 3.6V. For the SOT23 package, V_DD also defines the signal range of
the input signal AIN: 0V to VDD.
6
CS
Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal,
starts a conversion, and frames the serial data transfer.
—
CHSEL
Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to
select AIN1 for conversion.
—
OVDD ^{Digital Interface Supply for SCLK, CS, DOUT, and CHSEL. The OVDD range is 1.5V}
to VDD. Bypass OVDD with a 10FF || 0.1FF capacitor to GND.
5
DOUT
Three-State Serial Data Output. ADC conversion results are clocked out on the falling
edge of SCLK, MSB first. See Figure 1.
4
SCLK
Serial Clock Input. SCLK drives the conversion process. DOUT is updated on the fall-
ing edge of SCLK. See Figures 2 and 3.
EP
GND
Exposed Pad (TDFN and FMAX only). Connect EP directly to a solid ground plane.
Devices do not operate unless EP is connected to ground!
Maxim Integrated