MAX11102_12 Datasheet, PDF (14/30 Pages) Maxim Integrated Products – 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs

MAX11102/03/05/06/10/11/15/16/17
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11115/MAX11116) (continued)
(VDD = 2.2V to 3.6V. MAX11115: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11116: fSCLK = 48MHz, 50% duty cycle, 3Msps.
CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Digital Input Low Voltage
VIL
0.25 x
VDD
V
Digital Input Hysteresis
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
VHYST
IIL
CIN
Inputs at GND or VDD
0.15
VDD
V
0.001 Q1
FA
2
pF
Output High Voltage
VOH
ISOURCE = 200µA
0.85 x
VDD
V
Output Low Voltage
VOL
ISINK = 200µA
0.15 x
VDD
V
High-Impedance Leakage
Current
IOL
Q1.0
FA
High-Impedance Output
Capacitance
COUT
4
pF
POWER SUPPLY
Positive Supply Voltage
Positive Supply Current (Full-
Power Mode)
VDD
IVDD
Positive Supply Current (Full-
Power Mode), No Clock
IVDD
Power-Down Current
IPD
Line Rejection
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t_Q
CS Pulse Width
t1
CS Fall to SCLK Setup
t2
CS Falling Until DOUT High-
Impedance Disabled
t3
MAX11116, VAIN = VGND
MAX11115, VAIN = VGND
MAX11116
MAX11115
Leakage only
VDD = +2.2V to +3.6V
(Note 2)
(Note 2)
(Note 2)
(Note 2)
2.2
3.6
V
3.55
mA
2.6
1.98
mA
1.48
1.3
10
FA
0.17
LSB/V
4
ns
10
ns
5
ns
1
ns
Data Access Time After SCLK
Falling Edge
t4
Figure 2, VDD = +2.2V to +3.6V
15
ns
SCLK Pulse Width Low
t5
Percentage of clock period (Note 2)
40
SCLK Pulse Width High
t6
Percentage of clock period (Note 2)
40
Data Hold Time From SCLK
Falling Edge
t7
Figure 3
5
60
%
60
%
ns
SCLK Falling Until DOUT High-
Impedance
t8
Figure 4 (Note 2)
2.5
14
ns
Power-Up Time
Conversion cycle (Note 2)
1
Cycle
Note 1: All timing specifications given are with a 10pF capacitor.
Note 2: Guaranteed by design in characterization; not production tested.
14  
Maxim Integrated