MAX12559 Datasheet, PDF (19/30 Pages) Maxim Integrated Products – Dual, 96Msps, 14-Bit, IF/Baseband ADC

Dual, 96Msps, 14-Bit, IF/Baseband ADC
falling edge of DAV, and DAV rises once the output
data is valid. The falling edge of DAV is synchronized
to have a 5.8ns delay from the falling edge of the input
clock. Output data at D0A/B–D13A/B and DORA/B are
valid from 3.6ns before the rising edge of DAV to
3.55ns after the rising edge of DAV.
DAV enters high impedance when the MAX12559 is
powered down (PD = OV_DD). DAV enters its high-
impedance state 10ns after the rising edge of PD and
becomes active again 10ns after PD transitions low.
DAV can sink and source 600µA and has three times the
driving capabilities of D0A/B–D13A/B and DORA/B. DAV
is typically used to latch the MAX12559 output data into
an external digital back-end circuit. Keep the capacitive
load on DAV as low as possible (< 15pF) to avoid large
digital currents feeding back into the analog portion of
the MAX12559, thereby degrading its dynamic perfor-
mance. Buffering DAV externally isolates it from heavy
capacitive loads. Refer to the MAX12559 EV kit schemat-
ic for recommendations of how to drive the DAV signal
through an external buffer.
Data Out-of-Range Indicator
The DORA and DORB digital outputs indicate when the
analog input voltage is out of range. When DOR_ is high,
the analog input is out of range. When DOR_ is low, the
analog input is within range. The valid differential input
range is from (V_{REF_P} - V_{REF_N}) x 2/3 to (V_{REF_N} -
V_{REF_P}) x 2/3. Signals outside of this valid differential
range cause DOR_ to assert high as shown in Table 1.
DOR is synchronized with DAV and transitions along
with the output data D13_–D0_. There is an 8 clock-
cycle latency in the DOR function as is with the output
data (Figure 5). DOR_ is high impedance when the
MAX12559 is in power-down (PD = high). DOR_ enters
a high-impedance state within 10ns after the rising edge
of PD and becomes active 10ns after PD’s falling edge.
Digital Output Data and Output Format Selection
The MAX12559 provides two 14-bit, parallel, tri-state
output buses. D0A/B–D13A/B and DORA/B update on
the falling edge of DAV and are valid on the rising edge
of DAV.
Table 3. Output Codes vs. Input Voltage
GRAY-CODE OUTPUT CODE
(G/T = 1)
TWO’S-COMPLEMENT OUTPUT CODE
(G/T = 0)
BINARY
D13A–D0A
D13B–D0B
HEXADECIMAL
EQUIVALENT
DECIMAL
EQUIVALENT
DOR
OF
D13A–D0A
OF
D13A–D0A
D13B–D0B
D13B–D0B
(CODE₁₀)
BINARY
D13A–D0A
D13B–D0B
HEXADECIMAL
EQUIVALENT
DECIMAL
EQUIVALENT
DOR
OF
D13A–D0A
OF
D13A–D0A
D13B–D0B
D13B–D0B
(CODE₁₀)
10 0000 0000 0000 1
0x2000
+16,383 01 1111 1111 1111 1
0x1FFF
+8191
10 0000 0000 0000 0
10 0000 0000 0001 0
0x2000
0x2001
+16,383
+16,382
01 1111 1111 1111 0
01 1111 1111 1110 0
0x1FFF
0x1FFE
+8191
+8190
V_{IN_P} - V_{IN_N}
V_{REF_P} = 2.418V
V_{REF_N} = 0.882V
> +1.023875V
(DATA OUT OF
RANGE)
+1.023875V
+1.023750V
11 0000 0000 0011 0
11 0000 0000 0001 0
11 0000 0000 0000 0
01 0000 0000 0000 0
01 0000 0000 0001 0
0x3003
0x3001
0x3000
0x1000
0x1001
+8194
+8193
+8192
+8191
+8190
00 0000 0000 0010 0
00 0000 0000 0001 0
00 0000 0000 0000 0
11 1111 1111 1111 0
11 1111 1111 1110 0
0x0002
0x0001
0x0000
0x3FFF
0x3FFE
+2
+0.000250V
+1
+0.000125V
0
+0.000000V
-1
-0.000125V
-2
-0.000250V
00 0000 0000 0001 0
00 0000 0000 0000 0
00 0000 0000 0000 1
0x0001
0x0000
0x0000
+1
10 0000 0000 0001 0
0
10 0000 0000 0000 0
0
10 0000 0000 0000 1
0x2001
0x2000
0x2000
-8191
-8192
-8192
-1.023875V
-1.024000V
< -1.024000V
(DATA OUT OF
RANGE)
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