MAX12559 Datasheet, PDF (18/30 Pages) Maxim Integrated Products – Dual, 96Msps, 14-Bit, IF/Baseband ADC

Dual, 96Msps, 14-Bit, IF/Baseband ADC
V_DD
CLKP
CLKN
GND
S_1H
10kΩ
MAX12559
10kΩ
S_2H
S_1L
10kΩ
DUTY-CYCLE
EQUALIZER
10kΩ
SWITCHES S_{1_} AND S_{2_} ARE OPEN
S_2L DURING POWER-DOWN, MAKING
CLKP AND CLKN HIGH IMPEDANCE.
SWITCHES S_{2_} ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
Figure 4. Simplified Clock Input Circuit
and DIV2 high enables the divide-by-two feature, which
sets the sampling speed to one-half the selected clock
frequency. In divide-by-four mode, the converter sam-
pling speed is set to one-fourth the clock speed of the
MAX12559. Divide-by-four mode is achieved by applying
a high level to DIV4 and a low level to DIV2. The option to
select either one-half or one-fourth of the clock speed for
Table 2. Clock-Divider Control Inputs
DIV4
0
0
1
1
DIV2
0
1
0
1
FUNCTION
Clock Divider Disabled
f_SAMPLE = f_CLK
Divide-by-Two Clock Divider
f_SAMPLE = f_CLK / 2
Divide-by-Four Clock Divider
f_SAMPLE = f_CLK / 4
Not Allowed
sampling provides design flexibility, relaxes clock
requirements, and can minimize clock jitter.
System Timing Requirements
Figure 5 shows the timing relationship between the
clock, analog inputs, DAV indicator, DOR_ indicators,
and the resulting output data. The analog input is sam-
pled on the falling (rising) edge of CLKP (CLKN) and
the resulting data appears at the digital outputs 8 clock
cycles later.
The DAV indicator is synchronized with the digital out-
put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir-
cuitry can be latched with the rising edge of the con-
version clock (CLKP - CLKN).
Data-Valid Output
DAV is a single-ended version of the input clock that is
compensated to correct for any input clock duty-cycle
variations. The MAX12559 output data changes on the
DIFFERENTIAL ANALOG INPUT (IN_P - IN_N)
N+3
(V_{REF_P} - V_{REF_N})x2/3 N - 3 _{N - 2 N - 1}
N
N+1 ^N+2
N+4 N+5
(V_{REF_P} - V_{REF_N})x2/3
N+6
N+7
N+9
N+8
CLKN
t_AD
CLKP
t_DAV
DAV
D0_-D13_
DOR
t_CL
t_CH
t_SETUP
t_HOLD
N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9
8 CLOCK CYCLE DATA LATENCY
t_DATAHOLD
t_DATASETUP
Figure 5. System Timing Diagram
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