DS26514_11 Datasheet, PDF (174/305 Pages) Maxim Integrated Products – 4-Port T1/E1/J1 Transceiver Fully Internal Impedance Match, No External Resistor

DS26514 4-Port T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
RLS2 (T1 Mode)
Receive Latched Status Register 2
091h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
Name
—-
Default
0
6
5
4
3
2
1
—
COFA
8ZD
16ZD
SEFE
B8ZS
0
0
0
0
0
0
Note: All bits in these register are latched. This register does not create interrupts. See RLS2 for E1 Mode.
0
FBE
0
Bit 5: Change of Frame Alignment Event (COFA). Set when the last resync resulted in a change of frame or
multiframe alignment.
Bit 4: Eight Zero Detect Event (8ZD). Set when a string of at least eight consecutive zeros (regardless of the
length of the string) have been received at RRINGn and RTIPn.
Bit 3: Sixteen Zero Detect Event (16ZD). Set when a string of at least sixteen consecutive zeros (regardless of
the length of the string) have been received at RRINGn and RTIPn.
Bit 2: Severely Errored Framing Event (SEFE). Set when 2 out of 6 framing bits (Ft or FPS) are received in error.
Bit 1: B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RRINGn and RTIPn
independent of whether the B8ZS mode is selected or not. Useful for automatically setting the line coding.
Bit 0: Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
Register Name:
Register Description:
Register Address:
RLS2 (E1 Mode)
E1 Receive Latched Status Register 2
091h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
CRCRC CASRC FASRC
RSA1
RSA0
RCMF
RAF
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched. Bits 0 to 3 can cause interrupts. There is no associated real-time register. See RLS2
for T1 Mode.
Bit 6: CRC Resync Criteria Met Event (CRCRC). Set when 915:1000 codewords are received in error.
Bit 5: CAS Resync Criteria Met Event (CASRC). Set when 2 consecutive CAS MF alignment words are received
in error.
Bit 4: FAS Resync Criteria Met Event (FASRC). Set when 3 consecutive FAS words are received in error.
Bit 3: Receive Signaling All Ones Event (RSA1). Set when the contents of time slot 16 contains fewer than three
zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.
Bit 2: Receive Signaling All Zeros Event (RSA0). Set when over a full MF, time slot 16 contains all zeros.
Bit 1: Receive CRC-4 Multiframe Event (RCMF). Set on CRC-4 multiframe boundaries; will continue to be set
every 2ms on an arbitrary boundary if CRC-4 is disabled.
Bit 0: Receive Align Frame Event (RAF). Set approximately every 250µs to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
19-5856; Rev 4; 5/11
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