MAX1246_07 Datasheet, PDF (17/25 Pages) Maxim Integrated Products – 2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16

+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
CLOCK
MODE
SHDN
DIN
SETS EXTERNAL
CLOCK MODE
SXXXXX11
DOUT
12 DATA BITS
MODE
POWERED UP
EXTERNAL
EXTERNAL
SETS SOFTWARE
POWER-DOWN
SX X XXX0 0
SETS EXTERNAL
CLOCK MODE
S XX XXX1 1
12 DATA BITS
VALID
DATA
POWERED UP
SOFTWARE
POWER-DOWN
INVALID
DATA
HARDWARE
POWER-
DOWN
POWERED UP
Figure 11a. Timing Diagram Power-Down Modes, External Clock
CLOCK
MODE
DIN
DOUT
SETS INTERNAL
CLOCK MODE
SXXXXX10
INTERNAL
SETS
POWER-DOWN
SXXXXX0 0
DATA VALID
SSTRB
MODE
CONVERSION
POWERED UP
CONVERSION
S
DATA VALID
POWER-DOWN
POWERED UP
Figure 11b. Timing Diagram Power-Down Modes, Internal Clock
determines clock mode and power-down states. For
example, if the DIN word contains PD1 = 1, then the
chip remains powered up. If PD0 = PD1 = 0, a
power-down resumes after one conversion.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down (Table 6). Unlike software power-down
mode, the conversion is not completed; it stops coin-
cidentally with SHDN being brought low. SHDN also
controls the clock frequency in internal clock mode.
Letting SHDN float sets the internal clock frequency to
1.8MHz. When returning to normal operation with SHDN
floating, there is a t_RC delay of approximately 2MΩ x C_L,
where C_L is the capacitive loading on the SHDN pin.
Pulling SHDN high sets internal clock frequency to
225kHz. This feature eases the settling-time requirement
for the reference voltage. With an external reference, the
MAX1246/MAX1247 can be considered fully powered up
within 2µs of actively pulling SHDN high.
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