MAX1246_07 Datasheet, PDF (15/25 Pages) Maxim Integrated Products – 2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16

+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
The fastest the MAX1246/MAX1247 can run with CS held
low between conversions is 15 clocks per conversion.
Figure 10a shows the serial-interface timing necessary to
perform a conversion every 15 SCLK cycles in external
clock mode. If CS is tied low and SCLK is continuous,
guarantee a start bit by first clocking in 16 zeros.
Most microcontrollers (µCs) require that conversions
occur in multiples of 8 SCLK clocks; 16 clocks per con-
version is typically the fastest that a µC can drive the
MAX1246/MAX1247. Figure 10b shows the serial-
interface timing necessary to perform a conversion every
16 SCLK cycles in external clock mode.
CS
SSTRB
SCLK
t_CONV
t_CSH
t_SSTRB
PD0 CLOCK IN
DOUT
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 9. Internal Clock Mode SSTRB Detailed Timing
t_CSS
t_SCK
t_DO
CS
SCLK
DIN
DOUT
SSTRB
1
8
15 1
8
15 1
S
CONTROL BYTE 0
S
CONTROL BYTE 1
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
S CONTROL BYTE 2
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 1
Figure 10a. External Clock Mode, 15 Clocks/Conversion Timing
CS
1
8
SCLK
16
1
8
DIN
S CONTROL BYTE 0
S CONTROL BYTE 1
DOUT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
Figure 10b. External Clock Mode, 16 Clocks/Conversion Timing
•••
16
•••
•••
B11 B10 B9 B8 • • •
CONVERSION RESULT 1
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