MAX1393_09 Datasheet, PDF (16/18 Pages) Maxim Integrated Products – 1.5V to 3.6V, 312.5ksps, 1-Channel True-Differential/2-Channel Single-Ended, 12-Bit, SAR ADCs

1.5V to 3.6V, 312.5ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 12-Bit, SAR ADCs
Aperture Delay
The MAX1393/MAX1396 sample data on the falling
edge of its third SCLK cycle (Figure 14). In actuality,
there is a small delay between the falling edge of the
sampling clock and the actual sampling instant.
Aperture delay (t_AD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken.
Aperture Jitter
Aperture jitter (t_AJ) is the sample-to-sample variation in
the aperture delay (Figure 14).
DC Power-Supply Rejection Ratio (PSRR)
DC PSRR is defined as the change in the positive full-
scale transfer function point caused by a full range vari-
ation in the analog power-supply voltage (V_DD).
Chip Information
TRANSISTOR COUNT: 9106
PROCESS: BiCMOS
SCLK
ANALOG
INPUT
SAMPLED
DATA
T/H
(INTERNAL
SIGNAL)
TRACK
THIRD FALLING EDGE
t_AD
t_AJ
HOLD
Figure 14. T/H Aperture Timing
Typical Operating Circuit
2 x AA CELLS
0.1μF
REF
INPUT
VOLTAGE
0.1μF
DIFFERENTIAL ⁺
INPUT
VOLTAGE _-
V_DD
REF
OE
CS
MAX1393
AIN+ _MAX1396
(AIN1)*
SCLK
AIN-
(AIN2)*
DOUT
UNI/BIP
GND (CH1/CH2)*
CPU
SS
SCL
MISO
*INDICATES THE MAX1396 ONLY.
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