MAX1393_09 Datasheet, PDF (10/18 Pages) Maxim Integrated Products – 1.5V to 3.6V, 312.5ksps, 1-Channel True-Differential/2-Channel Single-Ended, 12-Bit, SAR ADCs

1.5V to 3.6V, 312.5ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 12-Bit, SAR ADCs
FS = V_REF
FFF
ZS = 0
FFE
1 LSB = ^VREF
4096
FFD
FFC
FFB
FULL-SCALE
TRANSITION
004
003
002
001
000
01234
FS
FS - 1.5 LSB
INPUT VOLTAGE (LSB)
Figure 5. Unipolar Transfer Function
Applications Information
Starting a Conversion
A falling edge on CS initiates the power-up sequence
and begins acquiring the analog input as long as OE is
also asserted low. On the 3rd SCLK falling edge, the
analog input is held for conversion. The most significant
bit (MSB) decision is made and clocked onto DOUT on
the 4th SCLK falling edge. Valid DOUT data is available
to be clocked into the master (microcontroller (μC)) on
the following SCLK rising edge. The rest of the bits are
decided and clocked out to DOUT on each successive
SCLK falling edge. See Figures 8 and 9 for conversion
timing diagrams.
Once a conversion has been initiated, CS can go high at
any time. Further falling edges of CS do not reinitiate an
acquisition cycle until the current conversion completes.
Once a conversion completes, the first falling edge of CS
begins another acquisition/conversion cycle.
+FS = ^VREF
7FF
2
ZS = 0
7FE
-FS = ^-VREF
2
001
1 LSB = ^VREF
4096
000
FFF
FFE
FULL-SCALE
TRANSITION
801
800
-FS
0
+FS
-FS + 0.5 LSB
+FS - 1.5 LSB
INPUT VOLTAGE (LSB)
Figure 6. Bipolar Transfer Function
Selecting Unipolar or Bipolar Mode
(MAX1393 Only)
Drive UNI/BIP high to select unipolar mode or pull
UNI/BIP low to select bipolar mode. UNI/BIP can be
connected to V_DD for logic high, to GND for logic low,
or actively driven. UNI/BIP needs to be stable for t_UBS
prior to the first rising edge of SCLK after the CS falling
edge (see Figure 1) for a valid conversion result when
being actively driven.
Selecting Analog Input AIN1 or AIN2
(MAX1396 Only)
Pull CH1/CH2 low to select AIN1 or drive CH1/CH2
high to select AIN2 for conversion. CH1/CH2 can be
connected to V_DD for logic high, to GND for logic low,
or actively driven. CH1/CH2 needs to be stable for t_CHS
prior to the first rising edge of SCLK after the CS falling
edge (see Figure 1) for a valid conversion result when
being actively driven.
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