MAX11606 Datasheet, PDF (16/22 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH INTERNAL CLOCK
1
7
11
S SLAVE ADDRESS R A CLOCK STRETCH
tACQ
tCONV
8
RESULT 2 MSBs A
8
RESULT 8 LSBs
11
A P or Sr
NUMBER OF BITS
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
7
11
S SLAVE ADDRESS R A
CLOCK STRETCH
tACQ1
tCONV1
tACQ2
tCONV2
8
1
8
1
CLOCK STRETCH RESULT 1 ( 2MSBs) A RESULT 1 (8 LSBs) A
tACQN
tCONVN
8
1
8
11
RESULT N (8MSBs) A RESULT N (8LSBs) A P or Sr
NUMBER OF BITS
Figure 10. Internal Clock Mode Read Cycles
The device memory contains all of the conversion results
when the MAX11606–MAX11611 release SCL. The con-
verted results are read back in a first-in-first-out (FIFO)
sequence. If AIN_/REF is set to be a reference input or
output (SEL1 = 1, Table 6), AIN_/REF is excluded from a
multichannel scan. This does not apply to the
MAX11608/MAX11609 as each provides separate pins
for AIN7 and REF. The memory contents can be read
continuously. If reading continues past the result stored
in memory, the pointer wraps around and point to the
first result. Note that only the current conversion results
are read from memory. The device must be addressed
with a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
7
11
8
1
8
S SLAVE ADDRESS R A RESULT (2 MSBs) A RESULT (8 LSBs)
11
A P OR Sr
t_ACQ
t_CONV
NUMBER OF BITS
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
7
11
8
1
8
1
S _{SLAVE ADDRESS} R A _{RESULT 1 (2 MSBs)} A _{RESULT 2 (8 LSBs)} A
8
1
8
11
RESULT N (2 MSBs) ^A RESULT N (8 LSBs) ^{A P OR Sr}
t_ACQ1
t_CONV1
t_ACQ2
t_ACQN
t_CONVN
Figure 11. External Clock Mode Read Cycle
16 ______________________________________________________________________________________
NUMBER OF BITS