MAX15038 Datasheet, PDF (15/18 Pages) Maxim Integrated Products – 4A, 2MHz Step-Down Regulator with Integrated Switches

4A, 2MHz Step-Down Regulator
with Integrated Switches
The high switching frequency range of the MAX15038
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
quency of the associated transfer function zero is higher
than the unity-gain crossover frequency, fC, and the zero
cannot be used to compensate for the double pole creat-
ed by the output filtering inductor and capacitor. The dou-
ble pole produces a gain drop of 40dB/decade and a
phase shift of 180°. The compensation network error
amplifier must compensate for this gain drop and phase
shift to achieve a stable high-bandwidth closed-loop sys-
tem. Therefore, use type III compensation as shown in
Figures 3 and 4. Type III compensation possesses three
poles and two zeros with the first pole, fP1_EA, located at
zero frequency (DC). Locations of other poles and zeros
of the type III compensation are given by:
f_{Z1_EA}
=
2π
×
1
R1
×
C1
f _{Z2 _ EA} =
2π
×
1
R3
×
C3
f_{P3 _ EA} =
2π
×
1
R1 ×
C2
f_{P2 _ EA} =
2π
×
1
R2
×
C3
The above equations are based on the assumptions
that C1 >> C2, and R3 >> R2, which are true in most
applications. Placements of these poles and zeros are
determined by the frequencies of the double pole and
ESR zero of the power transfer function. It is also a
function of the desired close-loop bandwidth. The fol-
lowing section outlines the step-by-step design proce-
dure to calculate the required compensation
components for the MAX15038. When the output volt-
age of the MAX15038 is programmed to a preset volt-
age, R3 is internal to the IC and R4 does not exist
(Figure 3b).
When externally programming the MAX15038 (Figure
3a), the output voltage is determined by:
R4
=
0.6×R3
(V_OUT −0.6)
(for
V_OUT
>
0.6V)
For a 0.6V output, connect an 80kΩ resistor from FB to
OUT. The zero-cross frequency of the close-loop, f_C
should be between 10% and 20% of the switching fre-
quency, f_S. A higher zero-cross frequency results in
faster transient response. Once f_C is chosen, C1 is cal-
culated from the following equation:
2.5 x ^VIN
C1
=
2
x
π
x
R3
x
V_{P − P}
(1+ ^RL
R_O
)
×
f_C
where V_P-P is the ramp peak-to-peak voltage (1V typ).
Due to the underdamped nature of the output LC double
pole, set the two zero frequencies of the type III compen-
sation less than the LC double-pole frequency to provide
adequate phase boost. Set the two zero frequencies to
80% of the LC double-pole frequency. Hence:
R1 = ¹ x ^{L x CO x (RO + ESR)}
0.8 x C1
R_L + R_O
C3 = ¹ x ^{L x CO x (RO + ESR)}
0.8 x R3
R_L + R_O
LX
MAX15038
OUT
CTL1
FB
CTL2
COMP
LX
MAX15038
OUT
VOLTAGE
SELECT
R3
8kΩ
FB
CTL1
COMP
CTL2
L
V_OUT
C_OUT
R2
R3
C3
R1 ^C1
R4
C2
a) EXTERNAL RESISTIVE DIVIDER
L
V_OUT
C_OUT
R2
C3
R1 ^C1
C2
b) INTERNAL PRESET VOLTAGES
Figure 3. Type III Compensation Network
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