MAX15023 Datasheet, PDF (15/28 Pages) Maxim Integrated Products – Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller

Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
Each PGOOD_ goes high (high impedance) when the
corresponding regulator output increases above 92.5%
of its nominal regulated voltage. Each PGOOD_ goes
low when the corresponding regulator output voltage
drops typically below 89.5% of its nominal regulated
voltage. PGOOD_ can be used as power-on-reset or
power sequencing for the two regulators.
PGOOD_ asserts low during the hiccup timeout period.
Startup into a Prebiased Output
When the controller starts into a prebiased output, the
DH_/DL_ complementary switching sequence is inhibit-
ed until the PWM comparator commands its first PWM
pulse. Until then, DH_ and DL_ are kept off so that the
converter does not sink current from the output. The
first PWM pulse occurs when the ramping reference
voltage increases above the FB_ voltage or the internal
soft-start time is over.
Current-Limit Circuit (LIM_)
The current-limit circuit employs a cycle-by-cycle low-
side source peak and sink current-sensing algorithm
that uses the on-resistance of the low-side MOSFET as
a current-sensing element, so that costly sense resis-
tors are not required. The current-limit circuit is also
temperature compensated to track the MOSFET’s on-
resistance variation over temperature. The current limit
is adjustable on each channel with an external resistor
at LIM_ (see the Typical Application Circuits), and
accommodates MOSFETs with a wide range of on-
resistance characteristics (see the Design Procedure
section). The adjustment range is from 30mV to 300mV
for the cycle-by-cycle, low-side, source peak current
limit, corresponding to resistor values of 6kΩ to 60kΩ.
The cycle-by-cycle, low-side, source peak current-limit
threshold across the low-side MOSFET is precisely 1/10
the voltage seen at LIM_, while the cycle-by-cycle, low-
side, sink peak current-limit threshold is 1/20 the volt-
age seen at LIM_.
The MAX15023 uses SGND to sense the voltage of the
source terminals of the low-side MOSFETs for both
channels, and LX_ to sense the drain voltage of each
low-side MOSFET. Carefully observe the PCB Layout
Guidelines section to ensure that noise and systematic
errors do not corrupt the current-sense signals seen by
LX_ and SGND on each channel.
Cycle-by-cycle, low-side, source peak current limit acts
when the inductor current flows in the normal direction,
and the drain (LX_) is more negative than source
(sensed by SGND) during the low-side MOSFET on-
time. If the magnitude of current-sense signal exceeds
the cycle-by-cycle, low-side, source peak current-limit
threshold during the low-side MOSFET on-time, the
controller does not initiate a new PWM cycle and lets
the inductor current decay in the next cycle. Since
cycle-by-cycle, low-side, source peak current sensing
is employed, the actual peak current is greater than the
current-limit threshold by an amount equal to the induc-
tor ripple current. Therefore, the exact current-limit
characteristic and maximum load capability are func-
tions of the low-side MOSFET’s on-resistance, current-
limit threshold, inductor value, and input voltage.
Cycle-by-cycle, low-side, sink peak current limit is also
implemented by monitoring the voltage drop across the
low-side MOSFET, but with opposite polarity (drain
more positive than source). If this drop exceeds 1/20
the voltage at the corresponding LIM_ pin at any time
during the low-side MOSFET on-time, the low-side
MOSFET is turned off and the inductor current flows
from the output through the high-side MOSFET back. If
the cycle-by-cycle, low-side, sink peak current limit is
activated, the DH_ and DL_ switching sequence is no
longer complementary.
Hiccup Mode Overcurrent Protection
Hiccup mode overcurrent protection reduces power
dissipation during prolonged short-circuit or deep over-
load conditions.
After the soft-start sequence has been completed, on
each switching cycle where the cycle-by-cycle, low-side,
source peak current-limit threshold is reached, a 3-bit
counter is incremented. The counter is decremented on
each switching cycle where the threshold is not reached,
and stopped at zero (000).
If the cycle-by-cycle, low-side, source peak current-
limit condition persists, the counter fills up reaching 111
(= 7 events). Then, the controller stops both DL_ and
DH_ drivers and waits for 7936 switching cycles (hic-
cup timeout delay). After this delay, the controller initi-
ates a new soft-start sequence.
If cycle-by-cycle, low-side, source peak current-limit
events occur during the soft-start time, turn-on cycles are
still skipped to control the inductor current, but the fill-up
of the 3-bit counter does not terminate the soft-start
sequence. Rather, the soft-start ramp is slowed down or
rolled back based on the cycle-by-cycle, low-side, source
peak current-limit events occurrences, so that the PWM
controller tries to regulate the inductor current around its
limit value, rather than the output voltage.
This proprietary technique prevents the duty cycle from
saturating, and limits the on-time and thus, the peak
inductor current is reached every time the high-side
MOSFET is turned on.
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