MAX1266 Datasheet, PDF (15/19 Pages) Maxim Integrated Products – 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 5. Full Scale and Zero Scale for Unipolar and Bipolar Operation
UNIPOLAR MODE
Full scale
Zero scale
—
V_REF + COM
COM
—
BIPOLAR MODE
Positive full scale
Zero scale
Negative full scale
V_REF/2 + COM
COM
-V_REF/2 + COM
OUTPUT CODE
111 . . . 111
111 . . . 110
100 . . . 010
100 . . . 001
100 . . . 000
011 . . . 111
011 . . . 110
011 . . . 101
FS = REF + COM
ZS = COM
1 LSB = ^REF
4096
FULL-SCALE
TRANSITION
000 . . . 001
000 . . . 000
0 12
(COM)
2048
INPUT VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 8. Unipolar Transfer Functions
Shutdown Mode
Shutdown mode turns off all chip functions that draw
quiescent current, reducing the typical supply current
to 2µA immediately after the current conversion is com-
pleted. A rising edge on WR causes the MAX1266/
MAX1268 to exit shutdown mode and return to normal
operation. To achieve full 12-bit accuracy with a 4.7µF
reference bypass capacitor, 500µs is required after
power-up. Waiting 500µs in standby mode, instead of
in full-power mode, can reduce power consumption by
a factor of 3 or more. When using an external refer-
ence, only 50µs is required after power-up. Enter
standby mode by performing a dummy conversion with
the control byte specifying standby mode.
Note: Bypass capacitors larger than 4.7µF between
REF and GND result in longer power-up delays.
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figures 8 depicts the nominal
OUTPUT CODE
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
FS = ^REF + COM
2
ZS = COM
-FS = ^-REF + COM
2
1 LSB = ^REF
4096
100 . . . 001
100 . . . 000
- FS
*COM ≥ V_REF / 2
COM*
INPUT VOLTAGE (LSB)
Figure 9. Bipolar Transfer Functions
+FS - 1 LSB
unipolar input/output (I/O) transfer function, and Figure 9
shows the bipolar I/O transfer function. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = (V_REF / 4096).
Maximum Sampling Rate/
Achieving 475ksps
When running at the maximum clock frequency of
7.6MHz, the specified throughput of 420ksps is
achieved by completing a conversion every 18 clock
cycles: 1 write cycle, 3 acquisition cycles, 13 conver-
sion cycles, and 1 read cycle. This assumes that the
results of the last conversion are read before the next
control byte is written. It is possible to achieve higher
throughputs, up to 475ksps, by first writing a control
byte to begin the acquisition cycle of the next conver-
sion, then reading the results of the previous conver-
sion from the bus. This technique (Figure 10) allows a
conversion to be completed every 16 clock cycles.
Note that the switching of the data bus during acquisi-
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