MAX1266 Datasheet, PDF (13/19 Pages) Maxim Integrated Products – 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
External Clock Mode
To select external clock mode, bits D6 and D7 of the
control byte must be set to 1. Figure 6 shows the clock
and WR timing relationship for internal (Figure 6a) and
external (Figure 6b) acquisition modes with an external
clock. For proper operation, a 100kHz to 7.6MHz clock
frequency with 30% to 70% duty cycle is recommended.
Operating the MAX1266/MAX1268 with clock frequen-
cies lower than 100kHz is not recommended, because
the resulting voltage droop across the hold capacitor in
the T/H stage degrades performance.
Digital Interface
The input and output data are multiplexed on a tri-state
parallel interface (I/O) that can easily be interfaced with
standard µPs. The signals CS, WR, and RD control the
write and read operations. CS represents the chip-
select signal, which enables a µP to address the
MAX1266/MAX1268 as an I/O port. When high, CS dis-
ables the CLK, WR, and RD inputs and forces the inter-
face into a high-impedance (high-Z) state.
CLK
WR
t_CWH
CLK
ACQUISITION STARTS
t_CP
ACQUISITION ENDS
CONVERSION STARTS
t_CWS ^tCH
t_CL
ACQMOD = 0
ACQUISITION STARTS
WR GOES HIGH WHEN CLK IS HIGH
ACQUISITION ENDS
CONVERSION STARTS
WR
ACQMOD = 0
WR GOES HIGH WHEN CLK IS LOW
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
t_DH
WR
ACQMOD = 1
WR GOES HIGH WHEN CLK IS HIGH
t_CWS
ACQMOD = 0
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
t_DH
WR
ACQMOD = 1
t_CWH
WR GOES HIGH WHEN CLK IS LOW
ACQMOD = 0
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
______________________________________________________________________________________ 13