MAX1266 Datasheet, PDF (10/19 Pages) Maxim Integrated Products – 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
A2
A1
A0
CH0
0
0
0
+
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
*Channels CH2–CH5 apply to MAX1266 only.
CH1
+
CH2*
CH3*
CH4*
+
+
+
CH5*
+
COM
-
-
-
-
-
-
Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
*Channels CH2–CH5 apply to MAX1266 only.
CH0
+
CH1
+
CH2*
+
CH3*
-
+
CH4*
+
-
CH5*
-
+
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C_HOLD. At
the end of the acquisition interval, the T/H switch
opens, retaining charge on C_HOLD as a sample of the
signal at IN+.
The conversion interval begins with the input multiplex-
er switching C_HOLD from the positive input (IN+) to the
negative input (IN-). This unbalances node zero at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node 0 to 0V within the
limits of 12-bit resolution. This action is equivalent to
transferring a 12pF [(V_IN+ - V_IN-)] charge from C_HOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to V_DD and GND, allow each input channel to
swing within (GND - 300mV) to (V_DD + 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (V_DD + 50mV) or be
less than (GND - 50mV).
If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current to
4mA.
Track/Hold
The MAX1266/MAX1268 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next on ris-
ing edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this is approximately 1µs after writing the control
byte.
In single-ended operation, IN- is connected to COM
and the converter samples the positive (+) input. In
pseudo-differential operation, IN- connects to the nega-
tive (-) input, and the difference of _|(IN+) - (IN-)_| is sam-
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and C_HOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
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