MAX1121 Datasheet, PDF (15/17 Pages) Maxim Integrated Products – 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
BYPASSING—ADC LEVEL
AV_CC
OV_CC
BYPASSING—BOARD LEVEL
AV_CC
0.1µF
0.1µF
1µF
10µF
47µF
AGND
OGND
D0P/N–D7P/N
OV_CC
MAX1121
8
1µF
10µF
47µF
AGND OGND
NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL)
SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1µF CAPACITOR CLOSE TO THE ADC.
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1121
ANALOG POWER-
SUPPLY SOURCE
DIGITAL/OUTPUT-
DRIVER POWER-
SUPPLY SOURCE
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. A major concern with this approach are the
dynamic currents that may need to travel long dis-
tances before they are recombined at a common
source ground, resulting in large and undesirable
ground loops. Ground loops can add to digital noise by
coupling back to the analog front end of the converter,
resulting in increased spur activity and a decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
effects of digital noise coupling, ground return vias can
be positioned throughout the layout to divert digital
switching currents away from the sensitive analog sec-
tions of the ADC. This does not require additional
ground splitting, but can be accomplished by placing
substantial ground connections between the analog
front end and the digital outputs.
The MAX1121 is packaged in a 68-pin QFN-EP pack-
age (package code: G6800-4), providing greater
design flexibility, increased thermal efficiency, and opti-
mized AC performance of the ADC. The EP must be
soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the PC board with standard infrared (IR)
flow soldering techniques.
Note that thermal efficiency is not the key factor, since
the MAX1121 features low-power operation. The
exposed pad is the key element to ensure a solid
ground connection between the DAC and the PC
board’s analog ground layer.
Considerable care must be taken, when routing the
digital output traces for a high-speed, high-resolution
data converter. It is essential to keep trace lengths at a
minimum and place minimal capacitive loading (less
than 5pF) on any digital trace to prevent coupling to
sensitive analog sections of the ADC. It is recommend-
ed to run the LVDS output traces as differential lines
with 100Ω characteristic impedance from the ADC to
the LVDS load device.
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