MAX1121 Datasheet, PDF (1/17 Pages) Maxim Integrated Products – 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

19-3077; Rev 1; 2/04
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
General Description
The MAX1121 is a monolithic 8-bit, 250Msps analog-to-
digital converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 250Msps while consuming only 477mW.
At 250Msps and an input frequency of 100MHz, the
MAX1121 achieves a spurious-free dynamic range
(SFDR) of 68dBc. Its excellent signal-to-noise ratio
(SNR) of 48.9dB at 10MHz remains flat (within 0.5dB)
for input tones up to 500MHz. This makes the MAX1121
ideal for wideband applications such as digital predis-
tortion in cellular base-station transceiver systems.
The MAX1121 requires a single 1.8V supply. The ana-
log input is designed for either differential or single-
ended operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock fre-
quencies as high as 500MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best perfor-
mance. The converter’s digital outputs are LVDS com-
patible, and the data format can be selected to be
either two’s complement or offset binary.
The MAX1121 is available in a 68-pin QFN with
exposed paddle (EP) and is specified over the industri-
al (-40°C to +85°C) temperature range.
For pin-compatible, higher resolution versions of the
MAX1121, refer to the MAX1122 (170Msps), the
MAX1123 (210Msps), and the MAX1124 (250Msps)
data sheets.
Applications
Wireless and Wired Broadband Communication
Digital Oscilloscopes
Digital Predistortion Receivers
Communications Test Equipment
Radar and Satellite Subsystems Antenna Array
Processing
Instrumentation
Features
♦ 250Msps Conversion Rate
♦ SNR = 48.8dB/48.7dB at f_IN = 100MHz/500MHz
♦ SFDR = 68dBc/63.8dBc at f_IN = 100MHz/500MHz
♦ Single 1.8V Supply
♦ 477mW Power Dissipation at 250Msps
♦ On-Chip Track-and-Hold and Internal Reference
♦ On-Chip Selectable Divide-by-2 Clock Input
♦ LVDS Digital Outputs with Data Clock Output
♦ Evaluation Kit Available (Order MAX1124EVKIT)
Ordering Information
PART
TEMP RANGE
MAX1121EGK
-40°C to +85°C
*EP = Exposed paddle.
PIN-PACKAGE
68 QFN-EP*
TOP VIEW
Pin Configuration
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
AVCC 1
AGND 2
EP
REFIO 3
REFADJ 4
AGND 5
AVCC 6
AGND 7
INP 8
INN 9
AGND 10
AVCC 11
AVCC 12
AVCC 13
AVCC 14
AGND 15
AGND 16
CLKDIV 17
MAX1121
51 D4P
50 D4N
49 D3P
48 D3N
47 D2P
46 D2N
45 OGND
44 OVCC
43 DCLKP
42 DCLKN
41 OVCC
40 D1P
39 D1N
38 D0P
37 D0N
36 N.C.
35 N.C.
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
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