MAX1121 Datasheet, PDF (13/17 Pages) Maxim Integrated Products – 1.8V, 8-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Applications Information
Full-Scale Range Adjustments Using the
Internal Bandgap Reference
The MAX1121 supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, an exter-
nal resistor value ranging from 13kΩ to 1MΩ may be
added between REFADJ and AGND. A similar
approach can be taken to increase the ADCs full-scale
range. Adding a variable resistor, potentiometer, or
predetermined resistor value between REFADJ and
REFIO increases the full-scale range of the data con-
verter. Figure 6 shows the two possible configurations
and their impact on the overall full-scale range adjust-
ment of the MAX1121. Do not use resistor values of less
than 13kΩ to avoid instability of the internal gain regula-
tion loop for the bandgap reference.
Differential, AC-Coupled, PECL-Compatible
Clock Input
The preferred method of clocking the MAX1121 is differ-
entially with LVDS- or PECL-compatible input levels. To
accomplish this, a 50Ω reverse-terminated clock signal
source with low phase noise is AC-coupled into a fast dif-
ferential receiver such as the MC100LVEL16 (Figure 7).
The receiver produces the necessary PECL output levels
to drive the clock inputs of the data converter.
ADC FULL-SCALE = REFT - REFB
REFT
REFB
REFERENCE-
SCALING
AMPLIFIER
G
REFERENCE
BUFFER
REFIO
1V
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
REFADJ
0.1µF
13kΩ
TO 1MΩ
13kΩ
TO 1MΩ
MAX1121
AV_CC AV_CC / 2
Figure 6. Circuit Suggestions to Adjust the ADC’s Full-Scale
Range
SINGLE-ENDED
INPUT TERMINAL ^0.1µF
50Ω
510Ω
V_CLK
0.1µF
8
7
2
MC100LVEL16
3
6
510Ω
4 _0.01µF 5
VGND
0.1µF
150Ω
0.1µF
150Ω
INP
INN
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
AV_CC OV_CC
CLKN CLKP
MAX1121
D0P/N–D7P/N
8
AGND OGND
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