MAX1300_10 Datasheet, PDF (14/32 Pages) Maxim Integrated Products – 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs

8- and 4-Channel, ±3 x V_REF Multirange Inputs,
Serial 16-Bit ADCs
Power Supplies
To maintain a low-noise environment, the MAX1300 and
MAX1301 provide separate power supplies for each
section of circuitry. Table 1 shows the four separate
power supplies. Achieve optimal performance using
separate AV_DD1, AV_DD2, DV_DD, and DV_DDO supplies.
Alternatively, connect AV_DD1, AV_DD2, and DV_DD
together as close to the device as possible for a conve-
nient power connection. Connect AGND1, AGND2,
AGND3, DGND, and DGNDO together as close to the
device as possible. Bypass each supply to the corre-
sponding ground using a 0.1μF capacitor (Table 1). If
significant low-frequency noise is present, add a 10μF
capacitor in parallel with the 0.1μF bypass capacitor.
Converter Operation
The MAX1300/MAX1301 ADCs feature a fully differen-
tial, successive-approximation register (SAR) conver-
sion technique and an on-chip T/H block to convert
voltage signals into a 16-bit digital result. Both single-
ended and differential configurations are supported
with programmable unipolar and bipolar signal ranges.
Track-and-Hold Circuitry
The MAX1300/MAX1301 feature a switched-capacitor
T/H architecture that allows the analog input signal to be
stored as charge on sampling capacitors. See Figures 2,
3, and 4 for T/H timing and the sampling instants for
each operating mode. The MAX1300/MAX1301 analog
input circuitry buffers the input signal from the sampling
capacitors, resulting in a constant input impedance with
varying input voltage (Figure 5).
Analog Input Circuitry
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2).
The analog input signal source must be capable of dri-
ving the ADC’s 17kΩ input resistance (Figure 6).
Figure 6 shows the simplified analog input circuit. The
analog inputs are ±16.5V fault tolerant and are protected
by back-to-back diodes. The summing junction voltage,
V_SJ, is a function of the channel’s input common-
mode voltage:
V_SJ
=
⎛ R1 ⎞
⎝⎜ R1 + R2⎠⎟
×
2.375V
+
⎛
⎝⎜¹⁺
⎛ R1 ⎞⎞
⎝⎜ R1 + R2⎠⎟⎠⎟
×
V_CM
As a result, the analog input impedance is relatively con-
stant over input voltage as shown in Figure 5.
Table 1. MAX1300/MAX1301 Power Supplies and Bypassing
POWER
SUPPLY/GROUND
DV_DDO/DGNDO
AV_DD2/AGND2
AV_DD1/AGND1
DV_DD/DGND
SUPPLY VOLTAGE
RANGE (V)
2.7 to 5.25
4.75 to 5.25
4.75 to 5.25
4.75 to 5.25
TYPICAL SUPPLY
CURRENT (mA)
0.03
135
3.0
0.8
CIRCUIT SECTION
Digital I/O
Analog Circuitry
Analog Circuitry
Digital Control Logic and Memory
BYPASSING
0.1μF to DGNDO
0.1μF to AGND2
0.1μF to AGND1
0.1μF to DGND
Table 2. Analog Input Configuration Byte
BIT
NUMBER
7
6
5
4
NAME
START
C2
C1
C0
DESCRIPTION
Start Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte.
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).
Differential or Single-Ended Configuration Bit. DIF/SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/SGL = 1 configures the channel for differential operation. In single-ended
3
DIF/SGL mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.
2
R2
1
R1
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.
0
R0
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