MAX1300_10 Datasheet, PDF (12/32 Pages) Maxim Integrated Products – 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs

8- and 4-Channel, ±3 x V_REF Multirange Inputs,
Serial 16-Bit ADCs
Pin Description
PIN
MAX1300 MAX1301
1
2
2
3
3
4
4
5
5
6
6
—
7
—
8
—
9
—
10
7
NAME
AV_DD1
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CS
FUNCTION
Analog Supply Voltage 1. Connect AV_DD1 to a +4.75V to +5.25V power-supply voltage. Bypass
AV_DD1 to AGND1 with a 0.1μF capacitor.
Analog Input Channel 0
Analog Input Channel 1
Analog Input Channel 2
Analog Input Channel 3
Analog Input Channel 4
Analog Input Channel 5
Analog Input Channel 6
Analog Input Channel 7
Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the
rising edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK.
When CS is high, activity on SCLK and DIN is ignored and DOUT is high impedance.
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8
DIN
Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is
high, transitions on DIN are ignored.
Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that
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SSTRB
data is ready to be read from the device. When operating in external clock mode, SSTRB is
always low. SSTRB does not tri-state, regardless of the state of CS, and therefore requires
a dedicated I/O line.
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10
SCLK
Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT.
When CS is high, transitions on SCLK are ignored.
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11
DOUT
Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK
transition. When CS is high, DOUT is high impedance.
15
12
DGNDO Digital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
16
13
DGND Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
17
14
DV_DDO
Digital I/O Supply Voltage Input. Connect DV_DDO to a +2.7V to +5.25V power-supply voltage.
Bypass DV_DDO to DGNDO with a 0.1μF capacitor.
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15
DV_DD
Digital-Supply Voltage Input. Connect DV_DD to a +4.75V to +5.25V power-supply voltage.
Bypass DV_DD to DGND with a 0.1μF capacitor.
Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AV_DD.
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REFCAP For internal reference operation, bypass REFCAP with a 0.01μF capacitor to AGND1
(V_REFCAP ≈ 4.096V).
Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an
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17
REF external reference voltage from 3.800V to 4.136V to REF. For internal reference operation,
bypassing REF with a 1μF capacitor to AGND1 sets V_REF = 4.096V ±1%.
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