MAX1282 Datasheet, PDF (14/24 Pages) Maxim Integrated Products – 300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference

300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Table 3. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
START
SEL2
SEL1
BIT 4
SEL0
BIT 3
UNI/BIP
BIT 2
SGL/DIF
BIT 1
PD1
BIT 0
(LSB)
PD0
BIT
7(MSB)
6
5
4
3
NAME
START
SEL2
SEL1
SEL0
UNI/BIP
2
SGL/DIF
1
PD1
0(LSB)
PD0
DESCRIPTION
The first logic 1 bit after CS goes low defines the beginning of the control byte.
These three bits select which of the eight channels are used for the conversion (Tables 1 and 2).
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0 to V_REF can be converted; in bipolar mode, the differential signal can
range from -V_REF/2 to +V_REF/2.
1 = single ended, 0 = pseudo-differential. Selects single-ended or pseudo-differential conver-
sions. In single-ended mode, input signal voltages are referred to COM. In pseudo-differential
mode, the voltage difference between two channels is measured (Tables 1 and 2).
Select operating mode.
PD1
PD0
Mode
0
0
Full power-down
0
1
Fast power-down
1
0
Reduced power
1
1
Normal operation
Table 4. Software-Controlled Power Modes
PD1/PD0
00
MODE
Full Power-Down
(FULLPD)
TOTAL SUPPLY CURRENT
CONVERTING
(mA)
AFTER
CONVERSION
2.5
2µA
CIRCUIT SECTIONS*
INPUT COMPARATOR
REFERENCE
Off
Off
01
Fast Power-Down
(FASTPD)
2.5
0.9mA
Reduced Power
On
10
Reduced-Power
Mode (REDP)
2.5
1.3mA
Reduced Power
On
11
Normal Operating
2.5
2.0mA
Full Power
On
*Circuit operation between conversions; during conversion all circuits are fully powered up.
Once conversion is completed, the device goes into the
programmed power mode until a new control byte is
written.
The power-up delay is dependent on the power-down
state. Software low-power modes will be able to start
conversion immediately when running at decreased
clock rates (see Power-Down Sequencing). Upon
power-on reset, when exiting software full power-down
mode, or when exiting hardware shutdown, the device
goes immediately into full-power mode and is ready to
convert after 2µs when using an external reference.
When using the internal reference, wait for the typical
power-up delay from a full power-down (software or
hardware) as shown in Figure 8.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. When software power-down is
asserted, the ADC completes the conversion in
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