MAX1282 Datasheet, PDF (10/24 Pages) Maxim Integrated Products – 300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference

300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Pin Description
PIN
NAME
FUNCTION
1
V_DD1
Positive Supply Voltage
2–5 CH0–CH3 Sampling Analog Inputs
6
COM
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
7
SHDN
Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA (typ).
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
8
REF
internal reference mode, the reference buffer provides a 2.500V nominal output, externally adjustable at
REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to V_DD1.
9
REFADJ Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to V_DD1.
10
GND
Ground
11
DOUT
Serial-Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.
12
SSTRB
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High impedance
when CS is high.
13
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
14
CS
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT and
SSTRB are high impedance.
15
SCLK
Serial-Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty cycle
must be 40% to 60%.)
16
V_DD2
Positive Supply Voltage
V_DD2
DOUT
3k
DOUT
3k
GND
C_LOAD
50pF
C_LOAD
50pF
GND
a) High-Z to V_OH and V_OL to V_OH
b) High-Z to V_OL and V_OH to V_OL
DOUT
3k
GND
V_DD2
3k
DOUT
C_LOAD
70pF
C_LOAD
20pF
GND
a) V_OH to High-Z
b) V_OL to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
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