MAX1182 Datasheet, PDF (14/21 Pages) Maxim Integrated Products – Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ANALOG INPUT
5 CLOCK-CYCLE LATENCY
N
N+1
N+2
N+3
N+4
N+5
N+6
CLOCK INPUT
DATA OUTPUT
D9A–D0A
DATA OUTPUT
D9B–D0B
t_D0
t_CH
t_CL
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
Figure 3. System Timing Diagram
OE
OUTPUT
D9A–D0A
OUTPUT
D9B–D0B
t_ENABLE
HIGH-Z
HIGH-Z
t_DISABLE
VALID DATA
VALID DATA
HIGH-Z
HIGH-Z
Figure 4. Output Timing Diagram
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V_DD/2 output voltage for level
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers, follows the
amplifiers. The user may select the R_ISO and C_IN val-
ues to optimize the filter performance, to suit a particu-
lar application. For the application in Figure 5, a R_ISO of
50Ω is placed before the capacitive load to prevent
ringing and oscillation. The 22pF C_IN capacitor acts as
a small bypassing capacitor.
Using Transformer Coupling
A RF transformer (Figure 6) provides an excellent solu-
tion to convert a single-ended source signal to a fully
differential signal, required by the MAX1182 for opti-
mum performance. Connecting the center tap of the
transformer to COM provides a V_DD/2 DC level shift to
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
In general, the MAX1182 provides better SFDR and
THD with fully-differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
14 ______________________________________________________________________________________