MAX1167_09 Datasheet, PDF (14/30 Pages) Maxim Integrated Products – Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters

Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
ANALOG
INPUTS
DIN
+5V
+5V
1μF
0.1μF
0.1μF
AIN0
CS
AIN1
SCLK
AIN2
DOUT
AIN3
EOC
DIN
REF ^MAX1167
AV_DD
DV_DD
AGND
AGND
DGND
REFCAP
CS
SCLK
DOUT
EOC
0.1μF
GND
Figure 5. MAX1167 Typical Operating Circuit
ANALOG
INPUTS
DIN
16
8
+5V
+5V
1μF
0.1μF
0.1μF
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
DIN
DSEL
DSPR
REF
AVDD
DVDD
CS
SCLK
DSPX
DOUT
EOC
MAX1168
AGND
AGND
DGND
REFCAP
CS
SCLK
DSPX
DOUT
EOC
0.1μF
GND
Figure 6. MAX1168 T ypical Operating Circuit
MUX
R_DSON
AIN_
C_MUX
TRACK
REF
CAPACITIVE
DAC
HOLD
C_SWITCH
C_DAC
AGND
HOLD
ZERO
R_IN
TRACK
AUTOZERO
RAIL
Figure 7. Equivalent Input Circuit
Digital Interface
The MAX1167/MAX1168 feature an SPI/QSPI/
MICROWIRE-compatible, 3-wire serial interface. The
MAX1167 digital interface consists of digital inputs CS,
SCLK, and DIN and outputs DOUT and EOC. The
MAX1167 operates in the following modes:
• SPI interface with external clock
• SPI interface with internal clock
• SPI interface with internal clock and scan mode
In addition to the standard 3-wire serial interface modes,
the MAX1168 includes a DSPR input and a DSPX output
for communicating with DSPs in external clock mode and
a DSEL input to determine 8-bit-wide or 16-bit-wide data-
transfer mode. When not using the MAX1168 in the DSP
interface mode, connect DSPR to DV_DD and leave DSPX
unconnected.
Command/Configuration/Control Register
Table 1 shows the contents of the command/configura-
tion/control register and the state of each bit after initial
power-up. Tables 2–6 define the control and configuration
of the device for each bit. Cycling the power supplies
resets the command/configuration/control register to the
power-on-reset default state.
Initialization After Power-Up
A logic high on CS places the MAX1167/MAX1168 in
the shutdown mode chosen by the power-down bits,
and places DOUT in a high-impedance state. Drive CS
low to power up and enable the MAX1167/MAX1168
before starting a conversion. In internal reference
mode, allow 5ms for the shutdown internal reference
and/or buffer to wake and stabilize before starting a
conversion. In external reference mode (or if the inter-
nal reference is already on), no reference settling time
is needed after power-up.
Table 1. Command/Configuration/Control Register
BIT7 (MSB) BIT6
BIT5
BIT4
COMMAND
CH SEL2 CH SEL1 CH SEL0 SCAN1
BIT3
SCAN0
POWER-UP
STATE
0
0
0
0
0
BIT2
REF/PD_SEL1
1
BIT1
REF/PD SEL0
1
BIT0 (LSB)
INT/EXT CLK
0
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