MAX1061 Datasheet, PDF (14/20 Pages) Maxim Integrated Products – 250ksps, +3V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface

250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
ACQUISITION STARTS
ACQUISITION ENDS
CLK
t_DH
WR
ACQMOD = 1
WR GOES HIGH WHEN CLK IS HIGH.
t_CWS
ACQMOD = 0
ACQUISITION STARTS
ACQUISITION ENDS
CLK
t_DH
WR
ACQMOD = 1
t_CWH
WR GOES HIGH WHEN CLK IS LOW. ACQMOD = 0
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
CONVERSION STARTS
CONVERSION STARTS
Table 2. Control Byte Format
D7 (MSB)
D6
D5
D4
D3
D2
PD1
PD0
ACQMOD
SGL/DIF
UNI/BIP
A2
D1
D0 (LSB)
A1
A0
Table 3. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
A2
A1
A0
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
0
0
0
+
0
0
1
+
0
1
0
+
0
1
1
+
1
0
0
+
1
0
1
+
1
1
0
+
1
1
1
*Channels CH4–CH7 apply to MAX1061 only.
CH7*
+
COM
-
-
-
-
-
-
-
-
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