MAX1106 Datasheet, PDF (13/16 Pages) Maxim Integrated Products – Single-Supply, Low-Power, Serial 8-Bit ADCs

Single-Supply, Low-Power,
Serial 8-Bit ADCs
CONVST
SCLK
DOUT
t_CSPW
t_DV
t_CONV
t_CH
t_CL
#1
t_DO
t_SCC
#8
t_DV
t_TR
Figure 7. Detailed Serial Interface Timing
data out of this register at any time after the conversion
is complete. After the eighth data-bit has clocked out,
DOUT goes high impedance and remains so with addi-
tional SCLKs.
Normally leave CONVST low until a new conversion
needs to be started. CONVST should be high for a
maximum of 100µs to maintain the 8-bit accuracy of the
Autozero Circuit.
The acquisition time, t_ACQ, starts immediately after the
end of conversion and a new conversion can be started
immediately after all data has been clocked out by tog-
gling CONVST high. Figure 8 shows a timing diagram
for a conversion at the data rate of 40ksps. Typically
20µs are necessary for the conversion to complete, 4µs
for reading the eight bits of data with a serial clock of
2MHz, and 1µs to complete the zero rail adjustment
and acquisition. The conversion time is guaranteed to
be less than 35µs, therefore the data rate should be
limited to 25ksps unless the conversion time for the
specific condition is known. Conversion time can be
determined by measuring the time between CONVST
falling edge and DOUT rising edge with a full-scale
input voltage.
__________Applications Information
Power-On Reset
When power is first applied with SHDN high or connect-
ed to V_DD, the MAX1106/MAX1107 is in track mode.
Conversion can be started by toggling CONVST high to
low as soon as the reference is settled when using the
internal reference, or after 20µs when an external refer-
ence is used. Powering up the MAX1106/MAX1107 with
t_CONV
CONVST
5V/div
SCLK
5V/div
DOUT
5V/div
5µs/div
Figure 8. 40ksps Timing Diagram
CONVST low will not start a conversion. No conversions
should be performed until the reference voltage (inter-
nal or external) has stabilized.
Shutdown Operation
Pulling SHDN low places the converter in low-current
power-down mode. In this state the converter draws
typically 0.5µA. In shutdown the analog biasing circuit
and the internal bandgap reference are powered down,
and DOUT goes high impedance.
The conversion stops coincidentally with SHDN going
low. If shutdown occurs during a conversion, power up,
wait 35µs, and clock SCLK eight times.
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