MAX1106 Datasheet, PDF (12/16 Pages) Maxim Integrated Products – Single-Supply, Low-Power, Serial 8-Bit ADCs

Single-Supply, Low-Power,
Serial 8-Bit ADCs
I/O
SCK
MISO
+3V
SS
a) SPI
CS
SCK
MISO
+3V
SS
b) QSPI
I/O
SK
SI
CONVST
SCLK
DOUT
MAX1106
MAX1107
CONVST
SCLK
DOUT
MAX1106
MAX1107
CONVST
SCLK
DOUT
c) MICROWIRE
MAX1106
MAX1107
Figure 5. Common Serial-Interface Connections
Starting SCLK before conversion is complete corrupts
the conversion in progress, and the data clocked out at
DOUT does not represent the input signal. Bringing
CONVST high at anytime during a conversion or while
the data is clocked out will result in an incorrect conver-
sion. A new conversion can be restarted only if all eight
data bits of conversion have been clocked out. Toggle
CONVST after all data is clocked out to restart a new
conversion.
SHDN is used to place the MAX1106/MAX1107 in low-
power mode (see Power-Down section). In this mode
DOUT is high impedance and any conversion in
progress is stopped immediately. If a conversion is
stopped by SHDN going low, the device must be reset
by waiting 35µs and clearing the output register with
eight SCLKs before the next conversion.
How to Perform a Conversion
The MAX1106/MAX1107 converts an input signal using
the internal clock. This frees the µP from the burden of
running the SAR conversion clock, and allows the con-
version results to be read back at the µP’s convenience
at any clock rate up to 2MHz.
Figures 6 and 7 show the serial interface timing charac-
teristics. CONVST idles low. Toggle CONVST high for at
least 1µs to perform the autozero adjustment. After
CONVST goes low, conversion starts immediately.
Allow 35µs for the internal conversion to complete and
issue the MSB of the conversion at DOUT. CONVST
needs to be held low once a conversion is started,
while SCLK should remain low during conversion for
best noise performance. An internal register stores data
when the conversion is in progress. SCLK clocks the
CONVST
t_CSPW
1µs
(MIN)
SCLK
HIGH-Z
DOUT
ACQ
A/D STATE
CONVERSION
t_CONV = 35µs (MAX)
100µs (MAX)
1
8
MSB
D7 D6
D5 D4
LSB
D3 D2 D1 D0
ACQUISITION
HIGH-Z
Figure 6. Conversion Timing Diagram
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