MAX1601 Datasheet, PDF (12/16 Pages) Maxim Integrated Products – Dual-Channel CardBus and PCMCIA Power Switches with SMBus™ Serial Interface

Dual-Channel CardBus and PCMCIA
Power Switches with SMBus™ Serial Interface
______SMBus™ Interface Operation
The SMBus serial interface is a two-wire interface with
multi-mastering capability, intended to control low-
speed peripheral devices in low-power portable equip-
ment applications. SMBus is similar to I²C™ and
AccessBus, but has slightly different logic threshold
voltage levels, different fixed addresses, and a sus-
pend-mode register capability. To obtain a complete
set of specifications on the SMBus interface, call Intel at
[phone] and ask for product code SBS5220.
SMBus Addressing
These dual-channel PC Card switch devices respond to
two of four different addresses, depending on the state
of the ADR address pin. Normal writing to the device is
done by transmitting one of four addresses, followed by
a single data byte, to program the channel selected.
Write transmissions to the interrupt pointer address are
not supported by these devices. Reading from the
device is done by transmitting one of two addresses cor-
Table 1. SMBus Addressing
SMB
ADDRESS
ADR PIN
0001100 Don’t care
1010000 Grounded
1010001 Grounded
1010010 Tied to VL
1010011 Tied to VL
WRITE
FUNCTION
N/A
Channel A
Channel B
Channel A
Channel B
READ FUNCTION
Interrupt Pointer
Channel A/B faults
Channel A/B faults
Channel A/B faults
Channel A/B faults
responding to either the A channel address (which will
provide data about faults for both A and B channels) or
to the interrupt pointer address (discussed later).
The normal start condition consists of a high-to-low
transition on SMBDATA while SMBCLK is high. The
7-bit address is followed by a bit that designates a read
or write operation: high = read, low = write. If the 7-bit
address matches one of the supported function
addresses, the IC issues an acknowledge pulse by
pulling the SMBDATA line low. If the address is not
valid, the IC stays off of the bus and ignores any data
on the bus until a new start condition is detected. Once
the IC receives a valid address that includes a write bit,
it expects to receive one additional byte of data. If a
stop condition or new start condition is detected before
a complete byte of data is clocked in, the IC interprets
this as an error and all of the data is rejected and lost.
SMBDATA and SMBCLK are Schmitt triggered and can
accommodate slower edges. However, rising edges
should still be faster than 1µs, and falling edges should
be faster than 300ns.
SMBus Write Operations
If the IC receives a valid address immediately followed
by a write bit, the IC becomes a slave receiver. The
slave IC generates a first acknowledge after the
address and write bit, and a second acknowledge after
the command byte. A stop condition following the com-
mand (data) byte causes immediate execution of the
command, unless the data included a low SUS/OP bit.
If the data included a low SUS/OP bit, the command is
stored in the suspend-mode register and is executed
only when the SMBSUS pin is pulled low (Figure 3).
Table 2. Command Format for Channel A Write Operations (address 1010000 or 1010010)
BIT
NAME POR STATE
FUNCTION
7 (MSB) OP/SUS
0
Operate/suspend bit. Selects which latch receives data: high = operation,
low = suspend.
6
VCCAON
0
Turns on VCCA when high, pulls VCCA to GND when low.
5
VCCA3/5
0
If VCCA is on, a high connects VY to VCCA, and a low connects VX to VCCA.
4
VCCAHIZ
0
Puts VCCA in a high-impedance state when high. Overrides VCCAON.
3
VPPAON
0
Turns on VPPA when high, pulls VPPA to GND when low.
2
VPPAPGM
0
If VPPA is on, a high connects VPPA to 12INA, and a low connects VPPA to VCCA.
1
VPPAHIZ
0
Puts VPPA in a high-impedance state when high. Overrides VPPAON.
0 (LSB) MASKFLT
0
Masks fault interrupts from both channel A and channel B when high.
I²C is a trademark of Philips Corp.
SMBus is a trademark of Intel Corp.
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