MAX14569 Datasheet, PDF (12/14 Pages) Maxim Integrated Products – Dual-Pair LLT with Charge Pump and High-ESD Protection

Dual-Pair LLT with Charge Pump
and High-ESD Protection
Shutdown Mode
The device features two enable inputs (ENAB, ENCD)
that place the device into a low-power shutdown mode
when both are driven low. If either ENAB or ENCD is
pulled high, the internal charge pump starts working and
generates 5V on VCC. When both ENAB and ENCD are
driven low, the MAX14569 enters shutdown mode and
draws a minimum current from VL and VBAT. To minimize
supply current in shutdown mode, connect INAVL and
INCVL to ground.
Charge Pump
The internal charge pump provides 5V on VCC when
VBAT is between 2.7V and 4.5V. When VBAT is between
2.3V and 2.7V, VCC is twice the voltage of VBAT. The
output is regulated to 5V as long as the battery voltage
supports it.
Thermal Protection
The device features thermal shutdown function neces-
sary to protect the device. When the junction tempera-
ture exceeds +150NC (typ), the charge pump turns off
and OUTAVCC, OUTBVL, OUTCVCC, OUTDVL are low.
This limits the device temperature from rising further.
When the temperature drops 20NC (typ) below +150NC
(typ), the device resumes normal operation.
Applications Information
Layout Recommendations
Use standard high-speed layout practices when laying
out a board with the device. For example, to minimize
line coupling, place all other signal lines not connected
to the device at least 1x the substrate height of the PCB
away from the input and output lines of the device.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass VL to ground with a 0.1FF ceramic capac-
itor, VBAT to ground with a 1FF ceramic capacitor, and
VCC to ground with a 2.2FF ceramic capacitor. Place
all capacitors as close as possible to the power-supply
inputs.
±25kV ESD Protection
As with all Maxim devices, ESD protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assem-
bly. The OUTAVCC, INBVCC, OUTCVCC, INDVCC pins
have extra protection against static electricity. Maxim’s
engineers have developed state-of-the-art structures to
protect these pins against ESD of Q25kV without dam-
age. The ESD structures withstand high ESD in all states:
normal operation, shutdown, and powered down. After
an ESD event, the device keeps working without latchup
or damage.
ESD protection can be tested in various ways. The
OUTAVCC, INBVCC, OUTCVCC, and INDVCC pins are
characterized for protection to the following limits:
U Q25kV using the Human Body Model
U Q15kV using the Air-Gap Discharge Method specified
in IEC 61000-4-2
U Q12kV using the Contact Discharge Method specified
in IEC 61000-4-2
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Human Body Model
Figure 3 shows the Human Body Model, and Figure 4
shows the current waveform it generates when dis-
charged into a low-impedance state. This model consists
of a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the test device through
a 1.5kI resistor.
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. It does not spe-
cifically refer to integrated circuits. The major difference
between tests done using the Human Body Model and
IEC 61000-4-2 is higher peak current in IEC 61000-4-2,
because series resistance is lower in the IEC 61000-4-2
model. Hence, the ESD withstand voltage measured to
IEC 61000-4-2 is generally lower than that measured
using the Human Body Model. Figure 5 shows the IEC
61000-4-2 model, and Figure 6 shows the current wave-
form for the Q8kV, IEC 61000-4-2, level 4, ESD Contact
Discharge Method.
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