MAX14569 Datasheet, PDF (10/14 Pages) Maxim Integrated Products – Dual-Pair LLT with Charge Pump and High-ESD Protection

Dual-Pair LLT with Charge Pump
and High-ESD Protection
TOP VIEW
V_L 1
ENAB 2
ENCD 3
INAVL 4
OUTBVL 5
INCVL 6
OUTDVL 7
GND 8
+
MAX14569
QSOP
16 CP1
15 VBAT
14 CP2
13 VCC
12 OUTAVCC
11 INBVCC
10 OUTCVCC
9 INDVCC
Pin Configuration
Pin Description
PIN
NAME
FUNCTION
1
VL
Logic Supply Voltage, +1.6V to +5.5V. Bypass VL to GND with a 0.1FF capacitor placed as close
as possible to the device.
2
ENAB
Enable Input for A and B Ports. Drive ENAB low for shutdown mode, or drive ENAB high for normal
operation.
3
ENCD
Enable Input for C and D Ports. Drive ENCD low for shutdown mode, or drive ENCD high for normal
operation.
4
INAVL Input A Port. Referenced to VL.
5
OUTBVL Output B Port. Referenced to VL.
6
INCVL Input C Port. Referenced to VL.
7
OUTDVL Output D Port. Referenced to VL.
8
GND
Ground
9
INDVCC Input D Port. Referenced to VCC.
10
OUTCVCC Output C Port. Referenced to VCC.
11
INBVCC Input B Port. Referenced to VCC.
12
OUTAVCC Output A Port. Referenced to VCC.
Charge-Pump Output. Bypass VCC to GND with a 2.2FF ceramic capacitor placed as close as
13
VCC
possible to the VCC pin to have high ESD protection on OUTAVCC, INBVCC, OUTCVCC, and
INDVCC pins.
14
CP2
External Charge-Pump Capacitor Connection
15
VBAT
Battery Input, +2.3V to +5.5V. Bypass VBAT to GND with a 1FF capacitor placed as close as
possible to the device.
16
CP1
External Charge-Pump Capacitor Connection
10