MAX1420 Datasheet, PDF (12/17 Pages) Maxim Integrated Products – 12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference

12-Bit, 60Msps, +3.3V, Low-Power ADC
INP
ADC
INN
A_VDD
10kΩ
CLK
10kΩ
CLK
AGND
Figure 4. Simplified Clock Input Circuit
D11–D0
10kΩ
10kΩ
MAX1420
Figure 4 shows a simplified model of the clock input cir-
cuit. This circuit consists of two 10kΩ resistors to bias
the common-mode level of each input. This circuit may
be used to AC-couple the system clock signal to the
MAX1420 clock input.
Output Enable (OE), Power-Down (PD)
and Output Data (D0–D11)
In addition to low operating power, the MAX1420 fea-
tures two power-down modes: reference power-down
and shutdown mode. In reference power-down, the in-
Table 1. MAX1420 Output Code for
Differential Inputs
DIFFERENTIAL DIFFERENTIAL
INPUT VOLTAGE*
INPUT
V_REF × 2047/2048
+FULL SCALE -
1LSB
V_REF × 2046/2048
+FULL SCALE -
2LSB
V_REF × 1/2048
0
+ 1 LSB
Bipolar Zero
-V_REF × 1/2048
- 1 LSB
-V_REF × 2046/2048
-FULL SCALE +
1 LSB
-V_REF × 2047/2048 -FULL SCALE
* V_REF = V_REFP - V_REFN
OFFSET
BINARY
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
OE
OUTPUT
DATA D11–D0
t_BE
HIGH-Z
VALID DATA
t_BD
HIGH-Z
Figure 5. Output Enable Timing
ternal bandgap reference is deactivated, which results in
a typical 2mA supply current reduction. A full shutdown
mode is available to maximize power savings during idle
periods.
The MAX1420 provides parallel, offset binary, CMOS-
compatible three-state outputs.
With OE high, the digital outputs enter a high-imped-
ance state. If OE is held low with PD high, the outputs
are latched at the last digital output code prior to the
power-down. All data outputs, D0 (LSB) through D11
(MSB), are TTL/CMOS logic-compatible. There is a
seven clock-cycle latency between any particular sam-
ple and its valid output data. The output coding is in off-
set binary format (Table 1).
The capacitive load on the digital outputs D0 through
D11 should be kept as low as possible (≤10pF), to
avoid large digital currents that could feed back into
the analog portion of the MAX1420, thereby degrading
its performance. The use of buffers (e.g., 74LVCH16244)
on the digital outputs of the ADC can further isolate the
digital outputs from heavy capacitive loads. To further
improve the dynamic performance of the MAX1420,
add small-series resistors of 100Ω to the digital output
paths, close to the ADC.
Figure 5 displays the timing relationship between out-
put enable and data output.
System Timing Requirements
Figure 6 depicts the relationship between the clock
input, analog input, and valid data output. The
MAX1420 samples the analog input signal on the rising
edge of CLK (falling edge of CLK) and output data is
valid seven clock cycles (latency) later.
Applications Information
Figure 7 depicts a typical application circuit containing
a single-ended to differential converter. The internal ref-
erence provides an AV_DD/2 output voltage for level
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. A lowpass filter at the
input suppresses some of the wideband noise associated
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