MAX1420 Datasheet, PDF (11/17 Pages) Maxim Integrated Products – 12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference

12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
AV_DD
R
R
50Ω
( ) CML
AV_DD
2
0.22µF
1nF
AV_DD
2
50Ω
MAX4284
( ) REFP
AV_DD
2
0.5V
R
0.22µF
1nF
R
AV_DD
2
MAX1420
AV_DD
4
R
50Ω
R
MAX4284
( ) REFN AVDD- 0.5V
2
0.22µF
1nF
AV_DD ^R
4
REFIN
R
AGND
0.5V
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
cations that require increased accuracy and a different
input voltage range.
The MAX1420 provides three modes of reference oper-
ation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, the on-chip +2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN are left floating. For stability purposes,
bypass REFIN, REFP, REFN and CML with a capacitor
network of 0.22µF in parallel with a 1nF capacitor to
AGND.
In buffered external reference mode, the reference volt-
age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
In unbuffered external reference mode, REFIN is con-
nected to AGND, thereby deactivating the on-chip
buffers of REFP, CML, and REFN. With their buffers
shut down, these nodes become high impedance and
can be driven by external reference sources, as shown
in Figure 3.
Clock Inputs (CLK, CLK)
The MAX1420’s CLK and CLK inputs accept both dif-
ferential and single-ended input operation and accept
CMOS-compatible clock signals. If CLK is driven with a
single-ended clock signal, bypass CLK with a 0.1µF
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (< 2ns). Sampling
occurs on the rising edge of the clock signal, requiring
this edge to have the lowest possible jitter. Any signifi-
cant aperture jitter would limit the SNR performance of
the ADC according to the following relationship:
SNR_dB
=
20 × log₁₀
2π
1
× f_IN
×
t_AJ
where f_IN represents the analog input frequency and
t_AJ is the aperture jitter. Clock jitter is especially critical
for high input frequency applications. The clock input
should always be considered as an analog signal and
routed away from any analog or digital signal lines.
The MAX1420 clock input operates with a voltage
threshold set to AV_DD/2. Clock inputs must meet the
specifications for high and low periods as stated in the
Electrical Characteristics.
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