MAX1420 Datasheet, PDF (10/17 Pages) Maxim Integrated Products – 12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference

12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
Detailed Description
The MAX1420 uses a 12-stage, fully-differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Each sample moves through a pipeline stage
every half-clock cycle, including the delay through the
output latch. The latency is seven clock cycles.
A 2-bit (2-comparator) flash ADC converts the held-
input voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held-input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage. This process is
repeated until the signal has been processed by all 12
stages. Each stage provides a 1-bit resolution. Digital
error correction compensates for ADC comparator off-
sets in each pipeline stage and ensures no missing
codes.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track-and-hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully-differential circuit
passes the input signal to the two capacitors C2a and
C2b through switches S4a and S4b. Switches S2a and
S2b set the common mode for the operational transcon-
ductance amplifier (OTA) input, and open simultane-
ously with S1, sampling the input waveform. The result-
ing differential voltage is held on capacitors C2a and
C2b. Switches S4a and S4b are then opened before
S3a, S3b, S4C are closed. The OTA is used to charge
capacitors C1a and C1b to the same values originally
held on C2a and C2b. This value is then presented to
the first stage quantizer and isolates the pipeline from
the fast-changing input. The wide input bandwidth T/H
amplifier allows the MAX1420 to track and sample/hold
analog inputs of high frequencies beyond Nyquist. The
analog inputs INP to INN can be driven either differen-
tially or single-ended. Match the impedance of INP and
INN and set the common-mode voltage to midsupply
(AV_DD/2) for optimum performance.
Analog Input and Reference Configuration
The full-scale range of the MAX1420 is determined by
the internally generated voltage difference between
REFP (AV_DD/2 + V_REFIN/4) and REFN (AV_DD/2 -
V_REFIN/4). The MAX1420’s full-scale range is adjustable
through REFIN, which provides high input impedance
for this purpose. REFP, CML (AV_DD/2), and REFN are
internally buffered low impedance outputs.
An internal +2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure accommodates an internal reference, or exter-
nally applied buffered or unbuffered reference for appli-
MDAC
V_IN
T/H
Σ
FLASH
ADC
DAC
2 BITS
x2
V_OUT
TO NEXT
STAGE
V_IN
STAGE 1
STAGE 2
STAGE 12
DIGITAL CORRECTION LOGIC
12
MAX1420
D11–D0
Figure 1. Pipelined Architecture—Stage Blocks
INTERNAL
BIAS
S2a
CML
S5a
C1a
S3a
S4a
OUT
C2a
S4c
S1
OTA
S4b
C2b
OUT
C1b
MAX1420
S2b
INTERNAL
BIAS
S3b
S5b
CML
Figure 2. Internal Track-and-Hold Circuit
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